Abstract: An electric motor system includes a battery, an inverter, an electric motor, a zero-phase switching arm and a control unit. The inverter converts DC power output from the battery into three-phase AC power and outputs the three-phase AC power to the electric motor. A rotor of the electric motor rotates by the three-phase AC power output from the inverter. A neural point of the electric motor is connected to the zero-phase switching arm. A zero-phase current flowing through respective windings of the electric motor is adjusted by switching of the zero-phase switching arm. By this means, in the electric motor system, torque is generated at the rotor also using the zero-phase current as well as a three-phase AC current flowing through the respective windings.

Abstract: A memory management unit includes a controller performing a process translating a requested virtual address to a physical address based on a first region storing first entries indicating the physical address matching a given bit range of the virtual address and a second region storing a second entry associating the bit range with the first entries. When a second entry matching the bit range of a first address is hit in the second region, the controller sets, in the hit second entry, an identification number of a first entry specified by the first address. When the same second entry regarding the first address and a second address is hit and when an identification number specified by the second address is larger than an identification number set in the second entry, the controller obtains, from a memory, information of first entries subsequent to first entries associated with the hit second entry.

Abstract: A memory management unit includes a controller performing a process translating a requested virtual address to a physical address based on a first region storing first entries indicating the physical address matching a given bit range of the virtual address and a second region storing a second entry associating the bit range with the first entries. When a second entry matching the bit range of a first address is hit in the second region, the controller sets, in the hit second entry, an identification number of a first entry specified by the first address. When the same second entry regarding the first address and a second address is hit and when an identification number specified by the second address is larger than an identification number set in the second entry, the controller obtains, from a memory, information of first entries subsequent to first entries associated with the hit second entry.

Abstract: A semiconductor device includes an address translation device configured to identify a plurality of address translation tables which is used for address translation having a plurality of stages; and an adder configured to identify a stage in the address translation when executing the address translation, wherein the address translation device configured to perform cache control for information of a first address translation table used in a last stage of the address translation when the stage is the final stage.

Abstract: A semiconductor device includes an address translation device configured to identify a plurality of address translation tables which is used for address translation having a plurality of stages; and an adder configured to identify a stage in the address translation when executing the address translation, wherein the address translation device configured to perform cache control for information of a first address translation table used in a last stage of the address translation when the stage is the final stage.

Abstract: A processor includes: a plurality of processor cores; an interconnector including a reduction operation device and configured to communicate with another processor; a memory controller configured to control a main memory; a bus configured to couple the plurality of processor cores, the interconnector, and the memory controller to each other; and a reduction operation buffer coupled to the bus and the interconnector, wherein each of the processor cores writes control information to control the reduction operation device included in the interconnector and a value to be operated by the reduction operation device in the reduction operation buffer, and the interconnector reads out the control information and the value from the reduction operation buffer and delivers the control information and the value to the reduction operation device.

Abstract: An information processing apparatus includes a plurality of processors and a plurality of links provided between the processors in a plurality of axis directions. Each of the processors includes a processor circuit, a memory, a memory controller, and an interconnect coupled to the processor circuit. The interconnect includes: a network switch configured to perform switching between the first links and a second link to its own processor; link counters provided to input links and output links of the first links and the second link respectively, the link counters being configured to count at least the number of packets passing through the input links and the output links; and a recorder configured to store count values of the link counters in the memory via the memory controller without a control by the processor circuit.

Abstract: An information processing apparatus includes a receiver to receive data-packets, the data-packets generated by dividing a message into division-data and storing, for each of the division-data, one of the plurality of division data into one of the plurality of data packets, wherein each of the data-packets also includes a data value indicating a quantity of the division-data and data indicating whether or not the data-packet includes final division data corresponding to an end of the message, a memory, and a processor to store the division-data that is contained in a packet of the data-packets that are received, in the memory, and suppress the final division-data from being stored in the memory until the quantity of the data-packets received by the receiver equates to the data value indicating the quantity of the division-data, in a case where the final division-data is received earlier than any one of the other division-data.

Abstract: A computation node device includes a buffer configured to store first data, a receiver configured to receive a packet including second data, an error check circuit configured to perform an error check of the packet and output a check result, and an operation device configured to perform, before receiving the check result output from the error check circuit, a reduction operation by using the first data stored in the buffer and the second data included in the packet and output an operation result of the reduction operation when the check result output from the error check circuit indicates non-existence of an error in the packet.

Abstract: An information processing apparatus includes a plurality of processors and a plurality of links provided between the processors in a plurality of axis directions. Each of the processors includes a processor circuit, a memory, a memory controller, and an interconnect coupled to the processor circuit. The interconnect includes: a network switch configured to perform switching between the first links and a second link to its own processor; link counters provided to input links and output links of the first links and the second link respectively, the link counters being configured to count at least the number of packets passing through the input links and the output links; and a recorder configured to store count values of the link counters in the memory via the memory controller without a control by the processor circuit.

Abstract: A processor includes: a plurality of processor cores; an interconnector including a reduction operation device and configured to communicate with another processor; a memory controller configured to control a main memory; a bus configured to couple the plurality of processor cores, the interconnector, and the memory controller to each other; and a reduction operation buffer coupled to the bus and the interconnector, wherein each of the processor cores writes control information to control the reduction operation device included in the interconnector and a value to be operated by the reduction operation device in the reduction operation buffer, and the interconnector reads out the control information and the value from the reduction operation buffer and delivers the control information and the value to the reduction operation device.

Abstract: A network interface device includes a direct memory access control unit (DMA); an address translation buffer (TLB) that stores address translation entries including a part of entries in an address translation table stored in the main memory; and a control unit that controls processing in relation to a command from the processor. The control unit, upon receiving a first command, transmits first transmission data including first message and remote node pre-caching TLB to a remote computer node, and upon receiving a second command, transmits write transmission data. And the remote computer node, in response to the first transmission data, pre-caches a first address translation entry in the TLB, and in response to the write transmission data, translates the remote node virtual address into a remote node real address based on the first address translation entry, and writes the write data to the main memory at the remote node real address.

Abstract: An information processing apparatus including: an arithmetic processing unit; and a communication device configured to receive data from another information processing apparatus through a plurality of first lanes and to output the received data to the arithmetic processing unit, wherein the communication device includes a detection unit that detects a failure of the plurality of first lanes; and a control unit that performs a first degradation process of stopping use of any one of the plurality of first lanes, based on a degradation request, performs a restoration process of resuming use of a first lane for which use has been stopped, based on a restoration request, and performs a second degradation process of stopping use of a first lane for which use has been resumed, when the detection unit detects a failure of the first lane for which use has been resumed, in the restoration process.

Abstract: A computation node device includes a buffer configured to store first data, a receiver configured to receive a packet including second data, an error check circuit configured to perform an error check of the packet and output a check result, and an operation device configured to perform, before receiving the check result output from the error check circuit, a reduction operation by using the first data stored in the buffer and the second data included in the packet and output an operation result of the reduction operation when the check result output from the error check circuit indicates non-existence of an error in the packet.

Abstract: An information processing apparatus includes a receiver to receive data-packets, the data-packets generated by dividing a message into division-data and storing, for each of the division-data, one of the plurality of division data into one of the plurality of data packets, wherein each of the data-packets also includes a data value indicating a quantity of the division-data and data indicating whether or not the data-packet includes final division data corresponding to an end of the message, a memory, and a processor to store the division-data that is contained in a packet of the data-packets that are received, in the memory, and suppress the final division-data from being stored in the memory until the quantity of the data-packets received by the receiver equates to the data value indicating the quantity of the division-data, in a case where the final division-data is received earlier than any one of the other division-data.

Abstract: An information processing apparatus includes: storage devices that store data; a data generation unit that generates padding-added data by adding padding to the data, based on adjustment information included in received data; and a storage processing unit that stores the padding-added data generated by the data generation unit in the storage devices. It is possible to shorten a latency even when non-aligned data is received.

Abstract: A communication apparatus includes a connection port and a processor. The connection port is connected to a switch apparatus. The processor is configured to acquire data to be transmitted to an external apparatus. The processor is configured to generate a packet destined to the external apparatus. The packet contains the data. The processor is configured to store the packet in a buffer. The processor is configured to acquire the packet from the buffer. The processor is configured to transmit the packet to the switch apparatus via the connection port. The processor is configured to acquire a state of a network to which the connection port is connected. The processor is configured to control, on basis of the state of the network and a predetermined packet generation time, a number of packets to be generated.

Abstract: An information processing device includes a transfer unit and an interface unit, the interface unit distributes transmission to a plurality of first lanes, and generate reception information from a plurality of pieces of distribution reception data received through a plurality of second lanes, the transfer unit includes a reception processing unit to extract reception data included in the reception information, and first error information indicating an error in any of the first lanes and a degeneration management unit to generate first degeneration information indicating a use stop lane among the first lanes, based on the first error information, generate second degeneration information indicating a use stop lane among the plurality of second lanes, based on second error information that is output from the interface unit, and cause the transmission processing unit to generate transmission information including the second degeneration information.

Abstract: A parallel computer includes a plurality of nodes. Each of the nodes includes a router directly or indirectly connected to each of the other nodes and a network interface connected to an external network of the parallel computer. The network interface includes a storage unit that holds detour route information indicating a detour route corresponding to a communication route from a node in which the network interface is included to another node. The network interface further includes a reception processing unit that, when the network interface receives data destined to one node of the parallel computer from the external network, sets detour route information corresponding to a communication route from the node in which the network interface is included to the destination node of the data for the data and transmits the data for which the detour route information is set to the destination node.

Abstract: A control method by an information processing system including a plurality of computers and a plurality of switch devices, the control method includes storing, by a first processor, degeneration information indicating a path in which a transmission rate is decreased and a decreasing ratio of a transmission rate in a first memory when a first switch device which include the first processor detects the path and the first switch device is set as a point of origin; determining, by a second processor, whether a plurality of packets pass through the path, based on the degeneration information when the plurality of packets are transmitted from a computer including the second processor; determining a length of a gap based on the decreasing ratio when it is determined that the plurality of packets pass through the path; and transmitting the plurality of packets with a transmission interval based on the length.