Patents by Inventor Shinya Hiramoto

Shinya Hiramoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10609188
    Abstract: An information processing apparatus includes a receiver to receive data-packets, the data-packets generated by dividing a message into division-data and storing, for each of the division-data, one of the plurality of division data into one of the plurality of data packets, wherein each of the data-packets also includes a data value indicating a quantity of the division-data and data indicating whether or not the data-packet includes final division data corresponding to an end of the message, a memory, and a processor to store the division-data that is contained in a packet of the data-packets that are received, in the memory, and suppress the final division-data from being stored in the memory until the quantity of the data-packets received by the receiver equates to the data value indicating the quantity of the division-data, in a case where the final division-data is received earlier than any one of the other division-data.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: March 31, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Shinya Hiramoto, Yuji Kondo, Yuichiro Ajima
  • Patent number: 10592299
    Abstract: A computation node device includes a buffer configured to store first data, a receiver configured to receive a packet including second data, an error check circuit configured to perform an error check of the packet and output a check result, and an operation device configured to perform, before receiving the check result output from the error check circuit, a reduction operation by using the first data stored in the buffer and the second data included in the packet and output an operation result of the reduction operation when the check result output from the error check circuit indicates non-existence of an error in the packet.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: March 17, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Yuji Kondo, Shinya Hiramoto, Yuichiro Ajima
  • Publication number: 20190334836
    Abstract: An information processing apparatus includes a plurality of processors and a plurality of links provided between the processors in a plurality of axis directions. Each of the processors includes a processor circuit, a memory, a memory controller, and an interconnect coupled to the processor circuit. The interconnect includes: a network switch configured to perform switching between the first links and a second link to its own processor; link counters provided to input links and output links of the first links and the second link respectively, the link counters being configured to count at least the number of packets passing through the input links and the output links; and a recorder configured to store count values of the link counters in the memory via the memory controller without a control by the processor circuit.
    Type: Application
    Filed: April 18, 2019
    Publication date: October 31, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Yuichiro Ajima, Shinya Hiramoto, YUJI KONDO
  • Publication number: 20190324927
    Abstract: A processor includes: a plurality of processor cores; an interconnector including a reduction operation device and configured to communicate with another processor; a memory controller configured to control a main memory; a bus configured to couple the plurality of processor cores, the interconnector, and the memory controller to each other; and a reduction operation buffer coupled to the bus and the interconnector, wherein each of the processor cores writes control information to control the reduction operation device included in the interconnector and a value to be operated by the reduction operation device in the reduction operation buffer, and the interconnector reads out the control information and the value from the reduction operation buffer and delivers the control information and the value to the reduction operation device.
    Type: Application
    Filed: March 21, 2019
    Publication date: October 24, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Yuichiro Ajima, Shinya Hiramoto, YUJI KONDO
  • Publication number: 20190286575
    Abstract: A network interface device includes a direct memory access control unit (DMA); an address translation buffer (TLB) that stores address translation entries including a part of entries in an address translation table stored in the main memory; and a control unit that controls processing in relation to a command from the processor. The control unit, upon receiving a first command, transmits first transmission data including first message and remote node pre-caching TLB to a remote computer node, and upon receiving a second command, transmits write transmission data. And the remote computer node, in response to the first transmission data, pre-caches a first address translation entry in the TLB, and in response to the write transmission data, translates the remote node virtual address into a remote node real address based on the first address translation entry, and writes the write data to the main memory at the remote node real address.
    Type: Application
    Filed: February 6, 2019
    Publication date: September 19, 2019
    Applicant: FUJITSU LIMITED
    Inventor: Shinya Hiramoto
  • Patent number: 10230625
    Abstract: An information processing apparatus including: an arithmetic processing unit; and a communication device configured to receive data from another information processing apparatus through a plurality of first lanes and to output the received data to the arithmetic processing unit, wherein the communication device includes a detection unit that detects a failure of the plurality of first lanes; and a control unit that performs a first degradation process of stopping use of any one of the plurality of first lanes, based on a degradation request, performs a restoration process of resuming use of a first lane for which use has been stopped, based on a restoration request, and performs a second degradation process of stopping use of a first lane for which use has been resumed, when the detection unit detects a failure of the first lane for which use has been resumed, in the restoration process.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: March 12, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Masahiro Maeda, Koichiro Takayama, Tomohiro Inoue, Shinya Hiramoto, Shun Ando, Yuichiro Ajima
  • Publication number: 20190073247
    Abstract: A computation node device includes a buffer configured to store first data, a receiver configured to receive a packet including second data, an error check circuit configured to perform an error check of the packet and output a check result, and an operation device configured to perform, before receiving the check result output from the error check circuit, a reduction operation by using the first data stored in the buffer and the second data included in the packet and output an operation result of the reduction operation when the check result output from the error check circuit indicates non-existence of an error in the packet.
    Type: Application
    Filed: August 6, 2018
    Publication date: March 7, 2019
    Applicant: FUJITSU LIMITED
    Inventors: YUJI KONDO, Shinya Hiramoto, Yuichiro Ajima
  • Publication number: 20180309859
    Abstract: An information processing apparatus includes a receiver to receive data-packets, the data-packets generated by dividing a message into division-data and storing, for each of the division-data, one of the plurality of division data into one of the plurality of data packets, wherein each of the data-packets also includes a data value indicating a quantity of the division-data and data indicating whether or not the data-packet includes final division data corresponding to an end of the message, a memory, and a processor to store the division-data that is contained in a packet of the data-packets that are received, in the memory, and suppress the final division-data from being stored in the memory until the quantity of the data-packets received by the receiver equates to the data value indicating the quantity of the division-data, in a case where the final division-data is received earlier than any one of the other division-data.
    Type: Application
    Filed: April 3, 2018
    Publication date: October 25, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Shinya Hiramoto, YUJI KONDO, Yuichiro Ajima
  • Patent number: 10002078
    Abstract: An information processing apparatus includes: storage devices that store data; a data generation unit that generates padding-added data by adding padding to the data, based on adjustment information included in received data; and a storage processing unit that stores the padding-added data generated by the data generation unit in the storage devices. It is possible to shorten a latency even when non-aligned data is received.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: June 19, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Shinya Hiramoto, Yuichiro Ajima, Tomohiro Inoue, Yuta Toyoda, Shun Ando, Masahiro Maeda
  • Patent number: 9893992
    Abstract: A communication apparatus includes a connection port and a processor. The connection port is connected to a switch apparatus. The processor is configured to acquire data to be transmitted to an external apparatus. The processor is configured to generate a packet destined to the external apparatus. The packet contains the data. The processor is configured to store the packet in a buffer. The processor is configured to acquire the packet from the buffer. The processor is configured to transmit the packet to the switch apparatus via the connection port. The processor is configured to acquire a state of a network to which the connection port is connected. The processor is configured to control, on basis of the state of the network and a predetermined packet generation time, a number of packets to be generated.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: February 13, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Shinya Hiramoto, Tomohiro Inoue, Shun Ando, Masahiro Maeda, Masao Yoshikawa
  • Patent number: 9755888
    Abstract: An information processing device includes a transfer unit and an interface unit, the interface unit distributes transmission to a plurality of first lanes, and generate reception information from a plurality of pieces of distribution reception data received through a plurality of second lanes, the transfer unit includes a reception processing unit to extract reception data included in the reception information, and first error information indicating an error in any of the first lanes and a degeneration management unit to generate first degeneration information indicating a use stop lane among the first lanes, based on the first error information, generate second degeneration information indicating a use stop lane among the plurality of second lanes, based on second error information that is output from the interface unit, and cause the transmission processing unit to generate transmission information including the second degeneration information.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: September 5, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Tomohiro Inoue, Shun Ando, Shinya Hiramoto, Masahiro Maeda, Masao Yoshikawa
  • Patent number: 9749222
    Abstract: A parallel computer includes a plurality of nodes. Each of the nodes includes a router directly or indirectly connected to each of the other nodes and a network interface connected to an external network of the parallel computer. The network interface includes a storage unit that holds detour route information indicating a detour route corresponding to a communication route from a node in which the network interface is included to another node. The network interface further includes a reception processing unit that, when the network interface receives data destined to one node of the parallel computer from the external network, sets detour route information corresponding to a communication route from the node in which the network interface is included to the destination node of the data for the data and transmits the data for which the detour route information is set to the destination node.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: August 29, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Tomohiro Inoue, Yuichiro Ajima, Shinya Hiramoto, Masahiro Maeda, Shun Ando, Yuta Toyoda
  • Patent number: 9641446
    Abstract: A control method by an information processing system including a plurality of computers and a plurality of switch devices, the control method includes storing, by a first processor, degeneration information indicating a path in which a transmission rate is decreased and a decreasing ratio of a transmission rate in a first memory when a first switch device which include the first processor detects the path and the first switch device is set as a point of origin; determining, by a second processor, whether a plurality of packets pass through the path, based on the degeneration information when the plurality of packets are transmitted from a computer including the second processor; determining a length of a gap based on the decreasing ratio when it is determined that the plurality of packets pass through the path; and transmitting the plurality of packets with a transmission interval based on the length.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: May 2, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Shinya Hiramoto, Tomohiro Inoue, Masahiro Maeda, Shun Ando
  • Patent number: 9619300
    Abstract: A reduction operation device detects a non-correspondence of an operation type or a data type in a reduction arithmetic operation of a parallel processing. The reduction operation device is inputted a plurality of the synchronization signals and data, sets each transmission destinations of the plurality of inputted synchronization signals and the plurality of data corresponding to a next stage of a reduction operation and executes the reduction operation. The synchronization unit in the reduction operation device detects the non-correspondence between the operation type or the data type included in an instruction of the reduction operation after the synchronization is established and controls the arithmetic operation of the arithmetic unit.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: April 11, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Shinya Hiramoto, Yuichiro Ajima, Tomohiro Inoue
  • Patent number: 9619347
    Abstract: An apparatus includes: a physical-layer device that distributes data to first lanes and performs data transfer to/from an external device by second lanes each of which has a number of the first lanes; and a transfer circuit that transfers data output by a central-processing unit performing arithmetic-processing to the physical-layer device and transfers the data received from the physical-layer device and received by the central-processing unit, the transfer circuit that comprises an information-acquisition unit that receives one of detection information of the first lanes which indicates that the physical-layer device has received data from the external device and error information of the first lanes which indicates that the data transferred to the physical-layer device from the external device has an error, from the physical-layer device, and a selection unit configured to specify the second lane to be degenerated based on one of the error information and the detection information.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: April 11, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Masahiro Maeda, Tomohiro Inoue, Shinya Hiramoto, Shun Ando, Koji Hosoe, Yuichiro Ajima
  • Patent number: 9542313
    Abstract: A parallel computer system includes information processing devices, each of the information processing devices including a communication control device that performs communication, a main memory that stores data, and an arithmetic processing device that is coupled to the communication control device and the main memory, the information processing devices being coupled to each other through a network by the respective communication control device, wherein the arithmetic processing device includes a cache memory and a cache controller, the cache controller that executes an atomic operation for target data on the cache memory that stores the target data when the communication control device outputs an atomic operation request that is used to request the atomic operation, the atomic operation being not divided into a smaller operation, and notifies the communication control device of a result that is obtained by executing the atomic operation on the cache memory.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: January 10, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Shinya Hiramoto, Tomohiro Inoue, Masahiro Maeda, Shun Ando, Yuta Toyoda
  • Patent number: 9426080
    Abstract: Provided is a data communication apparatus which includes a transmission interval calculator configured to calculate an effective transfer speed of the data based on a difference between an actual arrival time at which response data to transmission data transmitted to the other data communication apparatus has arrived and a predictive arrival time calculated by multiplying the number of relay devices passed until the response data from the other data communication apparatus arrives at the data communication apparatus by a transfer delay time necessary to pass through one relay device and a buffer size of the relay device on a communication path of the data, and calculate a transmission interval of transmission data based on the effective transfer speed and a transmission controller configured to perform transmission control of transmission data based on the transmission interval. Thus, congestion control is efficiently implemented in an interconnection network configured as a regular network.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: August 23, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Yuichiro Ajima, Tomohiro Inoue, Shinya Hiramoto
  • Patent number: 9385961
    Abstract: A parallel computing device includes a plurality of communicatively interconnected nodes for executing an arithmetic process. Each of the plurality of nodes includes: a measurement unit configured to measure a communication bandwidth up to a destination node based on a communication scheme among the nodes, and a control unit configured to control a size of a packet transmitted to the destination node according to the communication bandwidth measured by the measurement unit.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: July 5, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Shinya Hiramoto, Yuji Oinaga, Yuichiro Ajima, Tomohiro Inoue
  • Publication number: 20160191376
    Abstract: An information processing apparatus including: an arithmetic processing unit; and a communication device configured to receive data from another information processing apparatus through a plurality of first lanes and to output the received data to the arithmetic processing unit, wherein the communication device includes a detection unit that detects a failure of the plurality of first lanes; and a control unit that performs a first degradation process of stopping use of any one of the plurality of first lanes, based on a degradation request, performs a restoration process of resuming use of a first lane for which use has been stopped, based on a restoration request, and performs a second degradation process of stopping use of a first lane for which use has been resumed, when the detection unit detects a failure of the first lane for which use has been resumed, in the restoration process.
    Type: Application
    Filed: October 27, 2015
    Publication date: June 30, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Masahiro Maeda, Koichiro Takayama, Tomohiro Inoue, Shinya Hiramoto, Shun Ando, Yuichiro Ajima
  • Patent number: 9342473
    Abstract: A parallel computer system includes a plurality of processors including a first processor and a plurality of second processors; and a crossbar switch provided with a plurality of ports; wherein the first processor transmits data to a first port among the plurality of ports, and transmits standby time information to the first port in the case where the plurality of second processors are unable to transmit data to the first port despite receiving a communication authorization notification from the first port, and the first port receives the standby time information, and after the standby time elapses, selects one of the plurality of second processors.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: May 17, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Shun Ando, Shinya Hiramoto, Tomohiro Inoue, Yuta Toyoda, Masahiro Maeda, Yuichiro Ajima