Abstract: An apparatus includes: a physical-layer device that distributes data to first lanes and performs data transfer to/from an external device by second lanes each of which has a number of the first lanes; and a transfer circuit that transfers data output by a central-processing unit performing arithmetic-processing to the physical-layer device and transfers the data received from the physical-layer device and received by the central-processing unit, the transfer circuit that comprises an information-acquisition unit that receives one of detection information of the first lanes which indicates that the physical-layer device has received data from the external device and error information of the first lanes which indicates that the data transferred to the physical-layer device from the external device has an error, from the physical-layer device, and a selection unit configured to specify the second lane to be degenerated based on one of the error information and the detection information.

Abstract: A reduction operation device detects a non-correspondence of an operation type or a data type in a reduction arithmetic operation of a parallel processing. The reduction operation device is inputted a plurality of the synchronization signals and data, sets each transmission destinations of the plurality of inputted synchronization signals and the plurality of data corresponding to a next stage of a reduction operation and executes the reduction operation. The synchronization unit in the reduction operation device detects the non-correspondence between the operation type or the data type included in an instruction of the reduction operation after the synchronization is established and controls the arithmetic operation of the arithmetic unit.

Abstract: A parallel computer system includes information processing devices, each of the information processing devices including a communication control device that performs communication, a main memory that stores data, and an arithmetic processing device that is coupled to the communication control device and the main memory, the information processing devices being coupled to each other through a network by the respective communication control device, wherein the arithmetic processing device includes a cache memory and a cache controller, the cache controller that executes an atomic operation for target data on the cache memory that stores the target data when the communication control device outputs an atomic operation request that is used to request the atomic operation, the atomic operation being not divided into a smaller operation, and notifies the communication control device of a result that is obtained by executing the atomic operation on the cache memory.

Abstract: Provided is a data communication apparatus which includes a transmission interval calculator configured to calculate an effective transfer speed of the data based on a difference between an actual arrival time at which response data to transmission data transmitted to the other data communication apparatus has arrived and a predictive arrival time calculated by multiplying the number of relay devices passed until the response data from the other data communication apparatus arrives at the data communication apparatus by a transfer delay time necessary to pass through one relay device and a buffer size of the relay device on a communication path of the data, and calculate a transmission interval of transmission data based on the effective transfer speed and a transmission controller configured to perform transmission control of transmission data based on the transmission interval. Thus, congestion control is efficiently implemented in an interconnection network configured as a regular network.

Abstract: A parallel computing device includes a plurality of communicatively interconnected nodes for executing an arithmetic process. Each of the plurality of nodes includes: a measurement unit configured to measure a communication bandwidth up to a destination node based on a communication scheme among the nodes, and a control unit configured to control a size of a packet transmitted to the destination node according to the communication bandwidth measured by the measurement unit.

Abstract: An information processing apparatus including: an arithmetic processing unit; and a communication device configured to receive data from another information processing apparatus through a plurality of first lanes and to output the received data to the arithmetic processing unit, wherein the communication device includes a detection unit that detects a failure of the plurality of first lanes; and a control unit that performs a first degradation process of stopping use of any one of the plurality of first lanes, based on a degradation request, performs a restoration process of resuming use of a first lane for which use has been stopped, based on a restoration request, and performs a second degradation process of stopping use of a first lane for which use has been resumed, when the detection unit detects a failure of the first lane for which use has been resumed, in the restoration process.

Abstract: A parallel computer system includes a plurality of processors including a first processor and a plurality of second processors; and a crossbar switch provided with a plurality of ports; wherein the first processor transmits data to a first port among the plurality of ports, and transmits standby time information to the first port in the case where the plurality of second processors are unable to transmit data to the first port despite receiving a communication authorization notification from the first port, and the first port receives the standby time information, and after the standby time elapses, selects one of the plurality of second processors.

Abstract: A switch includes a plurality of ports and a combination determining unit that determines a central processing unit (CPU) to be paired with one of the ports. The port includes: an arbitration circuit that selects the CPU to be paired therewith when receiving an arbitration request from the CPU to be paired in a predetermined state, and selects one of the CPUs from which the arbitration request has been received in other cases to return transmission permission; and a data transfer unit that transfers the received data from the selected CPU to another CPU. The CPU includes: a request transmission unit that transmits the arbitration request to the ports; and a data transmission unit that transmits data to the paired port when the arbitration request is transmitted to the paired port in the predetermined state, and transmits data to the ports that have returned transmission permission in other cases.

Abstract: An information processing device includes a transfer unit and an interface unit, the interface unit distributes transmission to a plurality of first lanes, and generate reception information from a plurality of pieces of distribution reception data received through a plurality of second lanes, the transfer unit includes a reception processing unit to extract reception data included in the reception information, and first error information indicating an error in any of the first lanes and a degeneration management unit to generate first degeneration information indicating a use stop lane among the first lanes, based on the first error information, generate second degeneration information indicating a use stop lane among the plurality of second lanes, based on second error information that is output from the interface unit, and cause the transmission processing unit to generate transmission information including the second degeneration information.

Abstract: A communication apparatus includes a connection port and a processor. The connection port is connected to a switch apparatus. The processor is configured to acquire data to be transmitted to an external apparatus. The processor is configured to generate a packet destined to the external apparatus. The packet contains the data. The processor is configured to store the packet in a buffer. The processor is configured to acquire the packet from the buffer. The processor is configured to transmit the packet to the switch apparatus via the connection port. The processor is configured to acquire a state of a network to which the connection port is connected. The processor is configured to control, on basis of the state of the network and a predetermined packet generation time, a number of packets to be generated.

Abstract: In a case where data is output, a transmission node number stored by a transmission node number storing unit is updated. As a result of comparison between a transmission node number included in data input by an input unit and the transmission node number stored by the transmission node number storing unit, in a case where the transmission node number stored by the transmission node number storing unit is larger than the transmission node number included in the data input by the input unit, by overwriting the transmission node number included in data output by an output unit with the transmission node number stored in the transmission node number storing unit, congestion control matching the communication state of a communication route can be efficiently realized.

Abstract: A parallel computing system includes: each computing node including: a first channel receiving data which a preceding node transfers, and transferring received data to a subsequent node; a second channel receiving data which a preceding node transfers, and transferring received data to a subsequent node; and a computational processor receiving data which the first or second channel has received, and transferring processed data to a subsequent node; an input-output node including: a third channel receiving data which the first channel or the computational processor of a preceding node transfers; a fourth channel receiving data which the first channel or the computational processor of a preceding computing node transfers, and transferring the received data to the second channel of a subsequent computing node; and an input-output processor receiving data which the third channel has received, and transferring inputted and outputted data to the first channel of a subsequent computing node.

Abstract: An information processing apparatus included in a parallel computer system has a memory that holds data and a processor including a cache memory that holds a part of the data held on the memory and a processor core that performs arithmetic operations using the data held on the memory or the cache memory. Moreover, the information processing apparatus has a communication device that determines whether data received from a different information processing apparatus is data that the processor core waits for. When the communication device determines that the received data is data that the processor core waits for, the communication device stores the received data on the cache memory. When the communication device determines that the received data is data that the processor core does not wait for, the communication device stores the received data on the memory.

Abstract: An apparatus includes: a physical-layer device that distributes data to first lanes and performs data transfer to/from an external device by second lanes each of which has a number of the first lanes; and a transfer circuit that transfers data output by a central-processing unit performing arithmetic-processing to the physical-layer device and transfers the data received from the physical-layer device and received by the central-processing unit, the transfer circuit that comprises an information-acquisition unit that receives one of detection information of the first lanes which indicates that the physical-layer device has received data from the external device and error information of the first lanes which indicates that the data transferred to the physical-layer device from the external device has an error, from the physical-layer device, and a selection unit configured to specify the second lane to be degenerated based on one of the error information and the detection information.

Abstract: An information processing apparatus connected to another information apparatus in a parallel computer system via a plurality of routes, includes: an arithmetic processing device to issue an instruction for collection of congestion information and for communication; a route information holding unit to hold route information for performing communication; a transmission unit to transmit a congestion information collection packet to any of the plurality of routes; a reception unit to receive a congestion information collection response packet corresponding to the congestion information collection packet from any of the plurality of routes; and a control unit to cause the transmission unit to transmit a congestion information collection packet, to select route information from the route information holding unit based on congestion information included in the congestion information collection response packet, and to cause the transmission unit to perform communication instructed by the arithmetic processing device

Abstract: A control method by an information processing system including a plurality of computers and a plurality of switch devices, the control method includes storing, by a first processor, degeneration information indicating a path in which a transmission rate is decreased and a decreasing ratio of a transmission rate in a first memory when a first switch device which include the first processor detects the path and the first switch device is set as a point of origin; determining, by a second processor, whether a plurality of packets pass through the path, based on the degeneration information when the plurality of packets are transmitted from a computer including the second processor; determining a length of a gap based on the decreasing ratio when it is determined that the plurality of packets pass through the path; and transmitting the plurality of packets with a transmission interval based on the length.

Abstract: A parallel computer includes a plurality of nodes. Each of the nodes includes a router directly or indirectly connected to each of the other nodes and a network interface connected to an external network of the parallel computer. The network interface includes a storage unit that holds detour route information indicating a detour route corresponding to a communication route from a node in which the network interface is included to another node. The network interface further includes a reception processing unit that, when the network interface receives data destined to one node of the parallel computer from the external network, sets detour route information corresponding to a communication route from the node in which the network interface is included to the destination node of the data for the data and transmits the data for which the detour route information is set to the destination node.

Abstract: A synchronization apparatus includes a receiver that receives data from a synchronization apparatus of another node that performs synchronization with its own node from among the plurality of synchronization apparatuses and extracts synchronization information from the received data, a transmitter that transmits the data to the synchronization apparatus of the other node, a receiving state register that stores the extracted synchronization information, a delay unit that delays the received data by a specified period of time, and a controller that stores the extracted synchronization information and synchronization information from its own controller in the reception state register and causes the transmitter to transmit the data to the other node and returns the data to its own node back to its own controller via the delay unit when the extracted synchronization information and the synchronization information from its own controller are stored in the reception state register.

Abstract: An information processing apparatus includes: storage devices that store data; a data generation unit that generates padding-added data by adding padding to the data, based on adjustment information included in received data; and a storage processing unit that stores the padding-added data generated by the data generation unit in the storage devices. It is possible to shorten a latency even when non-aligned data is received.

Abstract: A parallel computer system includes information processing devices, each of the information processing devices including a communication control device that performs communication, a main memory that stores data, and an arithmetic processing device that is coupled to the communication control device and the main memory, the information processing devices being coupled to each other through a network by the respective communication control device, wherein the arithmetic processing device includes a cache memory and a cache controller, the cache controller that executes an atomic operation for target data on the cache memory that stores the target data when the communication control device outputs an atomic operation request that is used to request the atomic operation, the atomic operation being not divided into a smaller operation, and notifies the communication control device of a result that is obtained by executing the atomic operation on the cache memory.