Abstract: In a parallel computer system including a plurality of processors, processors are classified into a plurality of groups including a prescribed number of processors, and processors are connected to each other in a complete connecting manner in the groups. Those groups are connected to each other as the respective processors are connected in linear to each other.

Abstract: A network interface device is provided. The network interface device is connected to a computer and performs communications via a network includes a first management unit that identifies a communication connection by a port number, and manages a communication connection state of each port by a context that is stored in a storage unit and is associated with a port number, a second management unit that manages a storage state of the context, and a control unit that refers to the context, and performs an exemplary operation to establish a communication connection and an exemplary operation to cut off a communication connection between ports.

Abstract: A system has a plurality of nodes connected in a multi-dimensional matrix and having node addresses, respectively, each of the nodes having a processor, and a router for transmitting a request packet to a node adjacent to its own node located in n+1th dimension when the address of nth dimension of its own node is matched to the address of nth dimension of the target node, transmitting a response packet to a node adjacent to its own node located in nth dimension when the address of n+1th dimension of its own node is matched to the address of n+1th dimension of the response packet, wherein the router terminates a request packet when the address of the request packet is fully matched to the node address of its own node in all the dimensions, transfers the data conveyed by the request packet to the processor of its own node for processing.

Abstract: An I/O controller and method are provided. The I/O controller to which an I/O device can be connected, and instructs the I/O device to execute a process includes a descriptor transfer device that transfers a descriptor indicating contents of a process to be executed, and execution instruction unit that instructs the I/O device to execute the process, based on the descriptor transferred from the descriptor transfer device, wherein the descriptor transfer device includes a memory for storing the descriptor; descriptor reading unit that reads, according to an indication regarding a descriptor read source from a processor, an indicated descriptor from a main memory or said memory which stores the descriptor, and descriptor transfer unit that transfers the read descriptor to the execution instruction unit.

Abstract: A barrier synchronization apparatus includes a receiving device which transmits a first synchronization signal to a synchronization device when the first synchronization signal in which a transmission destination is set in advance according to setting conditions including an algorithm of the barrier synchronization and an execution condition is received. A synchronization device synchronizes n first synchronization signals which are set in advance according to the setting conditions, wherein n is a positive integer, and designates transmission of m second synchronization signals in which transmission destinations are set in advance according to the setting conditions after the synchronization is established, wherein m is a positive integer. A transmitting device transmits the second synchronization signals to m transmission destinations set in advance, when a transmission designation information indicating the transmission designation is received from the synchronization device.

Abstract: A system has a transmitter for transmitting a sequence of packets, the transmitter has a first counter for storing a first sequence number, a first generating unit for generating an error check code for checking an error in each of the packets on the basis of the header and the data in each of the packets and the first sequence number, and a transmitting unit for transmitting each of the packet together with each of the error check code and a receiver has a second counter for storing a second sequence number, a second generating unit for generating an error check code for checking an error in each of the packets on the basis of the header and the data in each of the packets received from the transmitter and the second sequence number and an error check unit for checking an error in the sequence of the packet.