Patents by Inventor Shinya Honda

Shinya Honda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140248733
    Abstract: The present invention provides a method of manufacturing a photoelectric conversion device for forming a semiconductor layer on a substrate by the plasma CVD method. The method includes a first plasma processing step in which a processing temperature reaches a first temperature; a second plasma processing step in which the processing temperature reaches a second temperature; a temperature regulating step of lowering the processing temperature to a third temperature lower than the first temperature and the second temperature after the first plasma processing step and before the second plasma processing step; and a temperature raising step of raising the processing temperature from the third temperature to the second temperature. The first plasma processing step, the temperature regulating step, the temperature raising step, and the second plasma processing step are carried out within the same reaction chamber.
    Type: Application
    Filed: September 27, 2012
    Publication date: September 4, 2014
    Inventors: Shinya Honda, Yoshiyuki Nasuno, Takashi Yamada, Kazuhito Nishimura
  • Publication number: 20140221613
    Abstract: The purpose of the present invention is: to provide an excellent protein which is further reduced in the binding property to an Fc region of an immunoglobulin and/or the binding property to an Fab region of the immunoglobulin in a weakly acidic region compared with that of a protein containing an extracellular domain of wild-type protein G, and which still keeps a high antibody-binding activity in a neutral region; and to capture and collect an antibody readily using the protein without denaturating the antibody.
    Type: Application
    Filed: August 3, 2012
    Publication date: August 7, 2014
    Inventors: Shinya Honda, Hiroyuki Matsumaru, Hideki Watababe, Chuya Yoshida
  • Patent number: 8776330
    Abstract: There is provided an end stop for a slide fastener, in which the attachment strength can be ensured irrespective of the size of the end stop, and a core can be firmly set to a setting position with respect to the end stop. The end stop has a base and a pair of legs which extend from the base, and the end stop is formed with a receptacle which is surrounded by the base and the pair of legs. The pair of legs have a pair of opening-side ends which are provided opposite to the base, and a pair of protrusions which are provided in the receptacle adjacent to the opening-side ends, the pair of protrusions protruding inward further than opposing surfaces of the pair of opening-side ends.
    Type: Grant
    Filed: December 25, 2009
    Date of Patent: July 15, 2014
    Assignee: YKK Corporation
    Inventors: Keiichi Keyaki, Shinya Honda
  • Publication number: 20140179898
    Abstract: A modified protein of an extracellular domain of protein A, which has the reduced ability to bind to immunoglobulin in an acidic region, compared with the wild-type extracellular domain of protein A, without impairing a selective antibody-binding activity in a neutral region. On the basis of three-dimensional structure coordinate data on a complex of the extracellular domain of protein A bound with the Fc region of immunoglobulin G, the modified protein is obtained by the substitution of amino acid residues that are located within the range of 10 angstroms from the Fc region and have a 20% or more ratio of exposed surface area, by histidine residues. Preferably, the modified protein is obtained by the substitution of amino acid residues at sites identified from the analysis of sequences selected from a library constituted by the protein group, by histidine residues. These substitutions may be combined.
    Type: Application
    Filed: December 3, 2013
    Publication date: June 26, 2014
    Applicant: NAT'L INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Shinya Honda, Hideki Watanabe, Masayuki Tsukamoto
  • Publication number: 20130255042
    Abstract: A slider for a slide fastener with an automatic stopper, includes a body forming an element guide passage into which fastener elements are insertable, a locking member swingably supported in the body by a pin and having a locking claw which is protrudable from a locking window hole formed in the body to the element guide passage and an urging member configured to urge the locking member so that the locking claw protrudes from the locking window hole to the element guide passage. A pair of lateral plate portions of the cover, which are disposed at both end portions of the pin are respectively provided with crimping protrusions which are abuttable against end faces of the pin and which are arranged at peripheral portions of a through-hole of the pair of lateral plate portions through which the pin penetrates.
    Type: Application
    Filed: September 24, 2010
    Publication date: October 3, 2013
    Applicant: YKK CORPORATION
    Inventors: Keiichi Keyaki, Koji Yamagishi, Shinya Honda
  • Patent number: 8450139
    Abstract: A method for manufacturing a photoelectric conversion device including a forming a semiconductor film by a plasma CVD method. The semiconductor film is an amorphous film of SiGe-based compound or a microcrystalline film of SiGe-based compound. The plasma CVD controls bandgap in thickness direction of the semiconductor film by varying the ON or OFF time of electric power applied to generate a plasma and intermittently supplying the power. The ON time and OFF time of the power fall in a range where the duty ratio ON time/(ON time+OFF time)×100(%) is 10% or more and 50% or less.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: May 28, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasuaki Ishikawa, Shinya Honda, Makoto Higashikawa
  • Publication number: 20120260470
    Abstract: There is provided an end stop for a slide fastener, in which the attachment strength can be ensured irrespective of the size of the end stop, and a core can be firmly set to a setting position with respect to the end stop. The end stop has a base and a pair of legs which extend from the base, and the end stop is formed with a receptacle which is surrounded by the base and the pair of legs. The pair of legs have a pair of opening-side ends which are provided opposite to the base, and a pair of protrusions which are provided in the receptacle adjacent to the opening-side ends, the pair of protrusions protruding inward further than opposing surfaces of the pair of opening-side ends.
    Type: Application
    Filed: December 25, 2009
    Publication date: October 18, 2012
    Applicant: YKK Corporation
    Inventors: Keiichi Keyaki, Shinya Honda
  • Publication number: 20120255147
    Abstract: A slide fastener slider has a body including an upper wing, a lower wing and a coupling pillar mutually coupling the respective upper and lower wings. The slide fastener slider has been cast molded to have a configuration where the post to which a pull is attached extends over the upper wing substantially in parallel with the upper wing, and then a logo or a pattern or the like has been engraved on the upper surface of the post.
    Type: Application
    Filed: December 25, 2009
    Publication date: October 11, 2012
    Applicant: YKK Corporation
    Inventors: Keiichi Keyaki, Shinya Honda
  • Publication number: 20120138134
    Abstract: A stack-type photovoltaic element with improved conversion efficiency having an intermediate layer and a method of manufacturing the same are provided. A stack-type photovoltaic element according to the present invention includes a first photovoltaic element portion (a) and a second photovoltaic element portion from a substrate side, as well as at least one intermediate layer between the first photovoltaic element portion and the second photovoltaic element portion. The intermediate layer is formed from a metal oxide film having an oxygen atom concentration/metal atom concentration ratio not lower than 0.956 and not higher than 0.976.
    Type: Application
    Filed: August 25, 2010
    Publication date: June 7, 2012
    Inventors: Makoto Higashikawa, Takako Shimizu, Shinya Honda, Yasuaki Ishikawa, Yuichi Sano
  • Publication number: 20120125406
    Abstract: Disclosed is a stacked photovoltaic element, including: a first photovoltaic element portion including at least one photovoltaic element, stacked over a substrate; an intermediate layer made of a metal oxide, stacked over the first photovoltaic element portion; a buffer layer in an amorphous state, stacked over the intermediate layer; and a second photovoltaic element portion including at least one photovoltaic element, stacked over the buffer layer, wherein a conductive layer of the second photovoltaic element portion in contact with the buffer layer is a microcrystalline layer.
    Type: Application
    Filed: August 4, 2010
    Publication date: May 24, 2012
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Makoto Higashikawa, Takako Shimizu, Shinya Honda, Yasuaki Ishikawa, Yuichi Sano
  • Publication number: 20120052619
    Abstract: A method for forming a semiconductor film suitable for a practical photoelectric conversion device having favorable photoelectric conversion efficiency and adapted to volume production and increased substrate area, and a method for manufacturing a photoelectric conversion device including the semiconductor film are provided. The method for forming a semiconductor film manufactures the semiconductor film including amorphous structure by a plasma CVD method. The semiconductor film is an amorphous film of SiGe-based compound or a microcrystalline film of SiGe-based compound. The plasma CVD method controls bandgap in thickness direction of the semiconductor film by varying the ON or OFF time of electric power applied to generate a plasma and intermittently supplying the power. The ON time and OFF time of the power fall in a range where the duty ratio ON time/(ON time+OFF time)×100(%) is 10% or more and 50% or less.
    Type: Application
    Filed: April 28, 2010
    Publication date: March 1, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yasuaki Ishikawa, Shinya Honda, Makoto Higashikawa
  • Patent number: 7853743
    Abstract: A processor includes: a plurality of processors; a process and status managing section which manages management information including information on statuses of the plurality of processors and priorities of processes being executed by the plurality of processors; a processing processor selecting section which selects one of the processors which is executing the process with a lowest priority on the basis of the management information managed by the process and status managing section; and an interrupt controlling section which transmits a requested interrupt process to the selected processor as an interrupt process request, wherein the processing processor selecting section selects the one of the processors, which is executing the process with the lowest priority, irrespective of whether each of the requested interrupt process and the processes being executed by the processors is a task process which is handled according to a predetermined schedule or an interrupt process which is handled independently of the
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: December 14, 2010
    Assignees: Seiko Epson Corporation, National University Corporation
    Inventors: Akinari Todoroki, Katsuya Tanaka, Hiroaki Takada, Shinya Honda
  • Patent number: 7702836
    Abstract: To provide a processor capable of achieving high processing efficiency by performing the exclusive control between task processing and interrupt handling properly even in a multiprocessor. An interrupt processor that includes a plurality of unit processors, in which at least of the plurality of unit processors is capable of performing interrupt handling requested from the outside is configured such that the unit processor P1 of the unit processors P0 to P3 comprises an purge inhibit flag 106 for causing the unit processor P1 to enter a lock state where the purge of the task is being inhibited, a hardware semaphore unit 13 for inhibiting other unit processors from accessing a predetermined region in memory accessed by the unit processor P1 after the unit processor P1 is brought into the lock state, and an interrupt control unit 11 for inhibiting the interrupt processor from performing the interrupt handling during the execution of exclusive control.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: April 20, 2010
    Assignees: Seiko Epson Corporation, National University Corporation Nagoya University
    Inventors: Akinari Todoroki, Akihiko Tamura, Katsuya Tanaka, Hiroaki Takada, Shinya Honda
  • Publication number: 20080288693
    Abstract: To provide a processor capable of achieving high processing efficiency by performing the exclusive control between task processing and interrupt handling properly even in a multiprocessor. An interrupt processor that includes a plurality of unit processors, in which at least of the plurality of unit processors is capable of performing interrupt handling requested from the outside is configured such that the unit processor P1 of the unit processors P0 to P3 comprises an purge inhibit flag 106 for causing the unit processor P1 to enter a lock state where the purge of the task is being inhibited, a hardware semaphore unit 13 for inhibiting other unit processors from accessing a predetermined region in memory accessed by the unit processor P1 after the unit processor P1 is brought into the lock state, and an interrupt control unit 11 for inhibiting the interrupt processor from performing the interrupt handling during the execution of exclusive control.
    Type: Application
    Filed: February 16, 2007
    Publication date: November 20, 2008
    Applicants: SEIKO EPSON CORPORATION, NATIONAL UNIVERSITY CORPORATION NAGOYA UNIVERSITY
    Inventors: Akinari Todoroki, Akihiko Tamura, Katsuya Tanaka, Hiroaki Takada, Shinya Honda
  • Publication number: 20080140896
    Abstract: A processor includes: a plurality of processors; a process and status managing section which manages management information including information on statuses of the plurality of processors and priorities of processes being executed by the plurality of processors; a processing processor selecting section which selects one of the processors which is executing the process with a lowest priority on the basis of the management information managed by the process and status managing section; and an interrupt controlling section which transmits a requested interrupt process to the selected processor as an interrupt process request, wherein the processing processor selecting section selects the one of the processors, which is executing the process with the lowest priority, irrespective of whether each of the requested interrupt process and the processes being executed by the processors is a task process which is handled according to a predetermined schedule or an interrupt process which is handled independently of the
    Type: Application
    Filed: November 1, 2007
    Publication date: June 12, 2008
    Applicants: SEIKO EPSON CORPORATION, NATIONAL UNIVERSITY CORPORATION NAGOYA UNIVERSITY
    Inventors: Akinari TODOROKI, Katsuya TANAKA, Hiroaki TAKADA, Shinya HONDA
  • Patent number: D656153
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: March 20, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Ken Imamura, Daisuke Kaguchi, Yutaka Tawara, Yoshinori Wakai, Eitaro Ito, Daisuke Nogami, Yuki Furuyama, Toshiyuki Moriwake, Shinya Honda, Junko Suzuki
  • Patent number: D709405
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: July 22, 2014
    Assignee: YKK Corporation
    Inventors: Keiichi Keyaki, Shinya Honda