Patents by Inventor Shinya Ishikawa

Shinya Ishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10651322
    Abstract: A solar cell element comprises a semiconductor substrate, a passivation layer, and first to third electrodes. The passivation layer with first holes is located on the semiconductor substrate. The first electrode is located in each of the first holes and electrically connected to the semiconductor substrate. The second electrode is electrically connected to the first electrode and located on the passivation layer. The third electrodes is electrically connected to the first electrode via the second electrode. The passivation layer includes a part where a ratio of an area occupied by the first holes in a first region adjacent to the third electrodes is smaller than a ratio of an area occupied by the first holes in a second region located farther away from the third electrodes in relation to the first region and having an area equal to an area of the first region in a perspective plan view.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: May 12, 2020
    Assignee: KYOCERA CORPORATION
    Inventor: Shinya Ishikawa
  • Publication number: 20200110257
    Abstract: An imaging unit includes: an optical system including a plurality of lenses; a prism configured to reflect light condensed by the optical system; a semiconductor package including an image sensor configured to generate an electrical signal by receiving light incident from the prism and performing photoelectric conversion on the received light, and including a connection electrode on a back surface of the semiconductor package; and a multi-layer substrate including a connection terminal on a top surface of the multi-layer substrate, the connection electrode being connected to the connection electrode via a conductive member. A concave portion in which an electronic component is mounted is formed in a region on a back surface of the multi-layer substrate, the region corresponding to a region where the connection terminal is formed.
    Type: Application
    Filed: December 10, 2019
    Publication date: April 9, 2020
    Applicant: OLYMPUS CORPORATION
    Inventors: Hiroyuki MOTOHARA, Shinya ISHIKAWA, Toshiyuki SHIMIZU
  • Publication number: 20200087768
    Abstract: Provided is a high-strength, heat-resistant, Ni-base alloy comprising Co: from 5 to 12%, Cr: from 5 to 12%, Mo: from 0.5 to 3.0%, W: from 3.0 to 6.0%, Al: from 5.5 to 7.2%, Ti: from 1.0 to 3.0%, Ta: from 1.5 to 6.0%, Re: from 0 to 2.0%, and C: from 0.01 to 0.20%. The high-strength, heat-resistant, Ni-base alloy is constituted of a Ni-based alloy, the balance of the Ni-based alloy comprising Ni and inevitable impurities. The density of the high-strength, heat-resistant Ni-base alloy is less than 8.5 g/cm3.
    Type: Application
    Filed: November 22, 2019
    Publication date: March 19, 2020
    Applicant: Mitsubishi Hitachi Power Systems, Ltd.
    Inventors: Masaki TANEIKE, Ikuo OKADA, Kazumasa TAKATA, Junichiro MASADA, Keizo TSUKAGOSHI, Hiroyuki YAMAZAKI, Yoshiaki NISHIMURA, Shinya ISHIKAWA
  • Publication number: 20200032395
    Abstract: A plasma processing method executed by a plasma processing apparatus in the present disclosure includes a first step and a second step. In the first step, the plasma processing apparatus forms a first film on the side walls of an opening in the processing target, the first film having different thicknesses along a spacing between pairs of side walls facing each other. In the second step, the plasma processing apparatus forms a second film by performing a film forming cycle once or more times after the first step, the second film having different thicknesses along the spacing between the pairs of side walls facing each other.
    Type: Application
    Filed: July 26, 2019
    Publication date: January 30, 2020
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Michiko NAKAYA, Toru HISAMATSU, Shinya ISHIKAWA, Sho KUMAKURA, Masanobu HONDA, Yoshihide KIHARA
  • Patent number: 10491756
    Abstract: An information processing apparatus includes: a first acquirer configured to acquire a first image displayed on a display in response to execution of an object program being a test object; an object image extractor configured to extract a partial image as an object image from the first image, based on first specification information specifying the partial image, the partial image being included in the first image and corresponding to a correct image; a determiner configured to determine whether or not the object image and the correct image accord; and a display processor configured to display a result of determination by the determiner.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: November 26, 2019
    Assignee: NS SOLUTIONS CORPORATION
    Inventors: Takuya Kashimura, Shinya Ishikawa, Marie Sakai, Masaru Yokoyama, Osamu Shimoda
  • Patent number: 10352244
    Abstract: A gas turbine combustor comprising a plurality of cooling air passages (27A) through which bled pressurized air flows from downstream of a combustion gas flow toward upstream, the plurality of cooling air passages (27A) being disposed in a wall portion (26) side by side and aligned in a flow direction of a combustion gas; wherein the plurality of cooling air passages (27A) are divided via a passage transition groove portion (33) into upstream cooling air passages (27A1) disposed closer to bled pressurized air inlet holes (30a) and downstream cooling air passages (27A2) disposed closer to bled pressurized air outlet holes (30b), and center lines (C1) of the upstream cooling air passages are non-collinear with center lines (C2) of the downstream cooling air passages.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: July 16, 2019
    Assignee: MITSUBISHI HITACHI POWER SYSTEMS, LTD.
    Inventors: Yoshiaki Yamaguchi, Satoshi Mizukami, Tomoyuki Hirata, Junichiro Masada, Tetsu Konishi, Kazumasa Takata, Hiroyuki Yamazaki, Takuya Suzuki, Shinya Ishikawa
  • Publication number: 20190198350
    Abstract: A method of processing a substrate is provided. The substrate includes an etching target region and a patterned region. The patterned region is provided on the etching target region. In the method, an organic film is formed on a surface of the substrate. Subsequently, the etching target region is etched by plasma generated from a processing gas. The organic film is formed in a state that the substrate is placed in a processing space within a chamber. When the organic film is formed, a first gas containing a first organic compound is supplied toward the substrate, and then, a second gas containing a second organic compound is supplied toward the substrate. An organic compound constituting the organic film is generated by polymerization of the first organic compound and the second organic compound.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 27, 2019
    Inventors: Masahiro Tabata, Toru Hisamatsu, Sho Kumakura, Ryuichi Asako, Shinya Ishikawa, Masanobu Honda
  • Patent number: 10263180
    Abstract: A magnetoresistance effect element includes a reference layer made of a ferromagnetic material, a recording layer made of a ferromagnetic material, and a barrier layer disposed between the reference layer and the recording layer. The reference layer and the recording layer have an in-plane magnetization direction parallel to a surface of the layers. The recording layer has a shape that has short axis and long axis perpendicular to the short axis in plan view. A first value obtained by dividing a thickness of the recording layer by a length of the short axis of the recording layer is greater than 0.3 and smaller than 1.
    Type: Grant
    Filed: July 22, 2017
    Date of Patent: April 16, 2019
    Assignee: TOHOKU UNIVERSITY
    Inventors: Hideo Sato, Shinya Ishikawa, Shunsuke Fukami, Shoji Ikeda, Fumihiro Matsukura, Hideo Ohno, Tetsuo Endoh
  • Patent number: 10245862
    Abstract: A power supply apparatus includes a power source unit configured to supply electric power to an electric load, a capacitor connected to a power supply line extending from the power supply unit to the electric load, a charge circuit configured to charge the capacitor while restricting a current value of the electric power supplied from the power source unit, a specifying unit configured to specify a voltage value of the capacitor, a first determination unit configured to determine whether the charge of the capacitor is completed in accordance with the voltage specified by the specifying unit, and a second determination unit configured to determine whether the voltage specified by the specifying unit is equal to or smaller than an error threshold value after the first determination unit determines that the charge of the capacitor is completed.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: April 2, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasufumi Ogasawara, Takashi Sakai, Hisao Okita, Shinya Ishikawa, Toru Oshika
  • Publication number: 20190081186
    Abstract: A solar cell element comprises a semiconductor substrate, a passivation layer, and first to third electrodes. The passivation layer with first holes is located on the semiconductor substrate. The first electrode is located in each of the first holes and electrically connected to the semiconductor substrate. The second electrode is electrically connected to the first electrode and located on the passivation layer. The third electrode is electrically connected to the first electrode via the second electrode. The passivation layer includes a part where a ratio of an area occupied by the first holes in a first region adjacent to the third electrode is smaller than a ratio of an area occupied by the first holes in a second region located farther away from the third electrode in relation to the first region and having an area equal to an area of the first region in a perspective plan view.
    Type: Application
    Filed: March 28, 2017
    Publication date: March 14, 2019
    Inventor: Shinya ISHIKAWA
  • Publication number: 20180294373
    Abstract: An insulation paste for forming a protective layer of a solar cell device includes: a siloxane resin; an organic solvent; and multiple fillers each having a surface covered with an organic coating containing at least one material different from a material of the siloxane resin. A method for producing the insulation paste includes: preparing the multiple fillers; and mixing together a precursor of the siloxane resin, water, a catalyst, an organic solvent, and the multiple fillers. A method for manufacturing a solar cell device includes: applying the insulation paste to the passivation layer; and drying the insulation paste to form the protective layer on the passivation layer. A solar cell device includes: the passivation layer located on a semiconductor region; and the protective layer located on the passivation layer and including a siloxane resin and dimethylpolysiloxane.
    Type: Application
    Filed: June 13, 2018
    Publication date: October 11, 2018
    Inventors: SHINYA ISHIKAWA, MOTOKI SHIBAHARA, SATOSHI KITAYAMA, DAISUKE OTA, TAKASHI KOIDE, TSUYOSHI KIMURA
  • Publication number: 20180179622
    Abstract: Provided is a high-strength, heat-resistant, Ni-base alloy comprising Co: from 5 to 12%, Cr: from 5 to 12%, Mo: from 0.5 to 3.0%, W: from 3.0 to 6.0%, Al: from 5.5 to 7.2%, Ti: from 1.0 to 3.0%, Ta: from 1.5 to 6.0%, Re: from 0 to 2.0%, and C: from 0.01 to 0.20%. The high-strength, heat-resistant, Ni-base alloy is constituted of a Ni-based alloy, the balance of the Ni-based alloy comprising Ni and inevitable impurities. The density of the high-strength, heat-resistant Ni-base alloy is less than 8.5 g/cm3.
    Type: Application
    Filed: July 5, 2016
    Publication date: June 28, 2018
    Applicant: MITSUBISHI HITACHI POWER SYSTEMS, LTD.
    Inventors: Masaki TANEIKE, Ikuo OKADA, Kazumasa TAKATA, Junichiro MASADA, Keizo TSUKAGOSHI, Hiroyuki YAMAZAKI, Yoshiaki NISHIMURA, Shinya ISHIKAWA
  • Publication number: 20180159988
    Abstract: An information processing apparatus includes: a first acquirer configured to acquire a first image displayed on a display in response to execution of an object program being a test object; an object image extractor configured to extract a partial image as an object image from the first image, based on first specification information specifying the partial image, the partial image being included in the first image and corresponding to a correct image; a determiner configured to determine whether or not the object image and the correct image accord; and a display processor configured to display a result of determination by the determiner.
    Type: Application
    Filed: May 31, 2016
    Publication date: June 7, 2018
    Inventors: Takuya KASHIMURA, Shinya ISHIKAWA, Marie SAKAI, Masaru YOKOYAMA, Osamu SHIMODA
  • Patent number: 9868282
    Abstract: A control apparatus including a power supply unit configured to supply electric power, comprises: a capacitor connected to a power supply line extending from the power supply unit to a printhead; a discharge circuit configured to release charge stored in the capacitor; and a control unit configured to control a current value during a discharge operation by the discharge circuit, such that the current value increases as a voltage value of the capacitor decreases.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: January 16, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Shinya Ishikawa, Yasufumi Ogasawara, Hisao Okita, Takashi Sakai, Toru Oshika
  • Patent number: 9862216
    Abstract: A power supply apparatus includes a power source unit supplying power to an electric load through a power supply line, a capacitor connected to the power supply line, a charge circuit charging the capacitor while restricting a current value of the power supplied from the power source unit, a detection unit detecting a voltage value of the capacitor, a controller which switches, after the charge of the capacitor is completed, a current value of the charge circuit to a first current value smaller than a current value supplied before the charge of the capacitor is completed, a first determination unit determining whether a first condition is satisfied based on the voltage value detected by the detection unit after the charge of the capacitor is completed, and a second determination unit determining whether an error process is to be performed based on a determination result of the first determination unit.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: January 9, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hisao Okita, Yasufumi Ogasawara, Takashi Sakai, Toru Oshika, Shinya Ishikawa
  • Publication number: 20170324030
    Abstract: A magnetoresistance effect element includes a reference layer made of a ferromagnetic material, a recording layer made of a ferromagnetic material, and a barrier layer disposed between the reference layer and the recording layer. The reference layer and the recording layer have an in-plane magnetization direction parallel to a surface of the layers. The recording layer has a shape that has short axis and long axis perpendicular to the short axis in plan view. A first value obtained by dividing a thickness of the recording layer by a length of the short axis of the recording layer is greater than 0.3 and smaller than 1.
    Type: Application
    Filed: July 22, 2017
    Publication date: November 9, 2017
    Applicant: TOHOKU UNIVERSITY
    Inventors: Hideo SATO, Shinya ISHIKAWA, Shunsuke FUKAMI, Shoji IKEDA, Fumihiro MATSUKURA, Hideo OHNO, Tetsuo ENDOH
  • Publication number: 20170294548
    Abstract: An insulating paste includes a siloxane resin and an organic solvent. The siloxane resin includes a phenyl group and an alkyl group expressed by a general formula CnH2n+1, in which n is a natural number. The number of alkyl groups is greater than the number of phenyl groups in the siloxane resin.
    Type: Application
    Filed: April 11, 2017
    Publication date: October 12, 2017
    Inventors: Jumpei SATO, Ryo MATSUOKA, Shinya ISHIKAWA
  • Publication number: 20170164818
    Abstract: An imaging unit includes: a semiconductor package having an image sensor and having a first connection electrode on a back face thereof; a first multi-layer substrate having layered substrates and having second and third connection electrodes respectively on front and back faces of the first multi-layer substrate, the second connection electrode being configured to be connected to the first connection electrode; a second multi-layer substrate having layered substrates, the second multi-layer substrate being configured to be connected to the back face of the first multi-layer substrate such that a layer direction of the second multi-layer substrate is perpendicular to a layer direction of the first multi-layer substrate; an electronic component mounted inside the first multi-layer substrate; and cables configured to be connected to the second multi-layer substrate. The first and second multi-layer substrates lie within a projected plane in an optical axis direction of the semiconductor package.
    Type: Application
    Filed: February 27, 2017
    Publication date: June 15, 2017
    Applicant: OLYMPUS CORPORATION
    Inventors: Shinya ISHIKAWA, Yuichi WATAYA, Akira MURAMATSU
  • Publication number: 20170150875
    Abstract: An imaging module includes: a chip size package having an image sensor that has a light receiving unit on a front side of the image sensor, the chip size package having connection lands on a back side of the image sensor; a circuit board having connection electrodes being electrically and mechanically connected to the connection lands of the chip size package through bumps; and an underfill material filled into a gap between the chip size package and the circuit board. The circuit board and the underfill material are provided within a projection plane on which the chip size package is projected in an optical axis direction of the image sensor. The circuit board has a cutout portion on a side surface thereof orthogonal to a connection surface of the circuit board with the chip size package such that the cutout portion is open to at least the connection surface.
    Type: Application
    Filed: February 14, 2017
    Publication date: June 1, 2017
    Applicant: OLYMPUS CORPORATION
    Inventors: Toshiyuki SHIMIZU, Hiroyuki MOTOHARA, Toshiyuki FUJII, Shinya ISHIKAWA
  • Patent number: 9592583
    Abstract: A polishing brush includes: a brush body that includes a cylindrical base section and linear abrasive materials extending from a bottom surface of one side of the base section along a direction of a center of an axis of the base section, and removes burrs and performs polishing on a surface of a workpiece metal by relatively moving the abrasive materials and the workpiece metal while tips of the abrasive materials come into contact with a surface of the workpiece metal; a brush guide that is coaxial with the center of the axis and is disposed on the outside of the brush body in a radial direction so that the tips of the abrasive materials protrude from an end portion; and a displacement mechanism that changes protruding lengths of the abrasive materials from the end portion.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: March 14, 2017
    Assignee: AISIN SEIKI KABUSHIKI KAISHA
    Inventors: Shinya Ishikawa, Michihiro Yamamoto, Satoru Shibata, Takamichi Hirasawa