Abstract: A method for fabricating a semiconductor device is provided in which a stress applied to each element formation region from each trench isolation region is sufficiently suppressed. The method is featured in that an insulating layer, which is to fill a trench selectively provided in a semiconductor substrate, is formed through at least two, separate deposition steps, and a heat treatment is performed after each deposition step. That is, first, a trench is formed on the silicon substrate and a insulating film is deposited in the trench on condition that the insulating film does not fully bury the trench. Then, a heat treatment is conducted. Finally, an insulating film is deposited in the trench to fully bury the trench, and subsequently the heat treatment is conducted.

Abstract: A method for an enhanced deposition control, comprises forming at least one device within a substrate of a semiconductor wafer, and depositing a silicon nitride layer over the wafer in a reactor at a pressure of at least approximately 104 Pa.

Abstract: A structure and manufacturing process of a low dielectric constant interlayer insulating film used between wiring layers and semiconductor devices using such film are disclosed. The insulating film which can withstand in an actual process comprises an amorphous carbon fluoride film. A diamond like carbon film and a silicon excess layer are disposed on both sides of the amorphous carbon fluoride film to be inserted between the wiring layers, whereby adhesion to wiring and another insulating film contacting it is significantly enhanced. In addition, a silicon based insulating film is disposed and flattened on a multilayer film containing an amorphous carbon fluoride film buried with a wiring layer, and is used as a hard mask for anisotropically etching the diamond like carbon film and the amorphous carbon fluoride film with oxygen plasma to form a via hole.

Abstract: The mass spectrum of a reference sample is stored at the time of preparing a calibration curve, and the mass spectrum of the reference sample that is stored is compared with the mass spectrum of an unknown sample at the time of measuring the unknown sample, in order to judge the reliability of the results of determination. Since the reliability of the results of determination is evaluated based on the numerical values, the evaluation does not change depending upon the judgment by the person who conducts the analysis, and certain evaluation is obtained.

Abstract: A method for fabricating a semiconductor device is provided in which a stress applied to each element formation region from each trench isolation region is sufficiently suppressed. The method is featured in that an insulating layer, which is to fill a trench selectively provided in a semiconductor substrate, is formed through at least two, separate deposition steps, and a heat treatment is performed after each deposition step. That is, first, a trench is formed on the silicon substrate and a insulating film is deposited in the trench on condition that the insulating film does not fully bury the trench. Then, a heat treatment is conducted. Finally, an insulating film is deposited in the trench to fully bury the trench, and subsequently the heat treatment is conducted.

Abstract: A method of manufacturing a semiconductor device having a wiring layer with an air bridge construction includes the steps of forming a lower layer metal interconnect, depositing an interlayer insulation film, depositing a first and a second insulation film, patterning the second insulation film and of etching the first insulation film and the interlayer insulation film using the second insulation film as a mask so as to form a post opening part and a via hole to connect an upper layer metal interconnect with the lower layer metal interconnect, depositing a third insulation film over the entire surface, etching back so as to leave the third insulation film in a side wall of the post opening part and fill the via hole with the third insulation film, depositing a fourth insulation film over the entire surface of the structure, then removing the fourth insulation film until the via hole is exposed, and then removing the third insulation film inside the via hole, filling the via hole with a metal, and then flatten

Abstract: After completion of wiring strips on an inter-level insulating structure, a field effect transistor is checked to see whether or not the threshold voltage falls within a design range, if the threshold voltage is out of the design range, hydrogen ion is implanted through the inter-level insulating structure, the gate electrode and the gate insulating layer into the channel region of the field effect transistor, and the resultant semiconductor structure is annealed at 400 degrees in centigrade for 20 minutes so as to partially deactivate the dopant impurity in the channel region.

Abstract: A structure and manufacturing process of a low dielectric constant interlayer insulating film used between wiring layers and semiconductor devices using such film are disclosed. The insulating film which can withstand in an actual process comprises an amorphous carbon fluoride film. A diamond like carbon film and a silicon excess layer are disposed on both sides of the amorphous carbon fluoride film to be inserted between the wiring layers, whereby adhesion to wiring and another insulating film contacting it is significantly enhanced. In addition, a silicon based insulating film is disposed and flattened on a multilayer film containing an amorphous carbon fluoride film buried with a wiring layer, and is used as a hard mask for anisotropically etching the diamond like carbon film and the amorphous carbon fluoride film with oxygen plasma to form a via hole.

Abstract: In producing a multilevel interconnection structure, an insulator film is placed on and bonded to interconnecting lines laid on an insulating layer on a semiconductor substrate such that all the spacings between the interconnecting lines are left as vacant spaces. For example, the insulator film is a polyimide film or a silicon oxide film. The vacant spaces serve the purpose of reducing capacitance between adjacent interconnecting lines. After forming contact holes in the insulator film and filling the contact holes with a metal, upper-level interconnecting lines are laid on the insulator film.

Abstract: A prescribed region of a polyacetylene film that is provided on the flattened surface of a first interlayer insulating film is doped so as to form an upper wiring layer on the polyacetylene film. A second interlayer insulating film which covers this polyacetylene film has a flattened surface which is formed by lamination of a polyimide film onto a silicon oxide film. A via hole is filled with a contact plug that is formed by a conductive polyacetylene film, and a prescribed region of a polyacetylene film that covers the second interlayer insulating film is doped to form an upper wiring layer of that polyacetylene film.

Abstract: In a method of manufacturing a semiconductor device, a conductive film is formed for a plurality of wiring patterns on a first insulating film and a second insulating film is formed on the conductive film. The second insulating film is patterned to be adaptive for the plurality of wiring patterns and then anisotropically etching is performed to the conductive film using the patterned second insulating film a mask such that a part of the conductive film is remained in a thickness direction of the conductive film. Subsequently, side wall insulating films are formed on side walls of the etched conductive film and then the conductive film is completely patterned for the plurality of wiring patterns using the side wall insulating films and the patterned second insulating film as a mask. In this case, the step of anisotropically etching the conductive film includes stopping the etching when the etching is performed by a predetermined depth with respect to a film thickness of the conductive film.

Abstract: An interlayer insulation layer is formed on a semiconductor substrate and a groove of a wiring shape is formed in the interlayer insulation layer. Then, the groove is buried with conductor. A part of the conductor is covered with a mask material, and a part of the conductor not covered with the mask is etched to form a recess. Thus, a first wiring is defined at a part of the conductor under the recess, and a columnar projection to be a connecting portion of wirings is defined at a side of the recess on the first wiring. An insulation layer is buried in the recess except for the upper surface of the columnar projection. A second wiring covering at least a part of the exposed upper surface of the columnar projection is formed.

Abstract: According to a process for producing .alpha.-phenylethyl alcohol by hydrogenation of acetophenone, which uses a copper-based catalyst containing at least one alkaline earth metal carbonate and/or at least one alkali metal compound, the hydrogenolysis of starting acetophenone is inhibited, and hence the production of ethylbenzene as a by-product is reduced, so that it becomes possible to produce .alpha.-phenylethyl alcohol useful as a starting material for styrene with high selectivity.

Abstract: In a process for manufacturing a semiconductor device, on a surface including interconnections selectively formed on an insulating film, an interlayer insulating film to have a thickness thicker than that of the interconnections is deposited. A positive type photoresist is deposited, and then, exposed through a mask having a regular stripe pattern extending over the whole of the mask, while causing an exposing light to focus on a low altitude region of the interlayer insulating film. The photoresist is developed, with the result that a regular pattern of the developed photoresist is formed on only a low altitude region. A second resist is deposited on a surface including the first resist so as to cause the second resist to have a substantially planarized surface. Then, an etch-back is performed for a whole surface at least until a surface of the low altitude region of the interlayer insulating film is exposed, whereby an upper surface of the interlayer insulating film is planarized.

Abstract: A porous filter having a pore size of no more than 80 .mu.m is provided in a refrigerant flow passage of a refrigeration system. The filter may be provided in a drier provided in the refrigerant flow passage or in a separate filter casing provided in the refrigerant flow passage. Alternatively, the filter may be provided in the refrigerant flow passage within a sealed casing of a refrigerant compressor which is incorporated in the refrigeration system. The filter is formed of a molded solid material constituted by alumina, silica gel, calcium sulfide and aluminosilicate.

Abstract: A porous filter having a pore size of no more than 80 .mu.m is provided in a refrigerant flow passage of a refrigeration system. The filter may be provided in a drier provided in the refrigerant flow passage or in a separate filter casing provided in the refrigerant flow passage. Alternatively, the filter may be provided in the refrigerant flow passage within a sealed casing of a refrigerant compressor which is incorporated in the refrigeration system.