Abstract: A semiconductor device includes an interlayer insulating film in which first contact holes and second contact holes are provided. Each of the second contact holes has a width narrower than a width of the corresponding first contact hole. A contact plug is located in the corresponding second contact hole. An upper electrode layer is arranged on an upper surface of the interlayer insulating film, upper surfaces of the contact plugs, and inner surfaces of the first contact holes. The protective insulating film covers an upper surface of the external field. An end portion extending along a direction intersecting with the plurality of trenches of the protective insulating film extends through a range located above the plurality of the second contact holes. A pillar region is in contact with the upper electrode layer in the first contact hole.

Abstract: An electric device system includes a first unit and a second unit adjacent to each other. An elastically deformable first connecting terminal is provided in the first unit, and a second connecting terminal is provided in the second unit. When the first unit is assembled in the second unit, the first connecting terminal comes into contact with the second connecting terminal after sliding on an outer surface of a casing of the second unit. A bulging surface is provided in an exposed surface of the first connecting terminal, and a recess is provided in an exposed surface of the second connecting terminal. A part of the bulging surface and a part of an opening edge of the recess come into press-contact with each other by fitting a part of the bulging surface in the recess, thereby establishing electric conduction between the first connecting terminal and the second connecting terminal.

Abstract: A semiconductor device comprises a conductive layer, a first insulating film, a barrier metal, a contact electrode, and a surface electrode. The first insulating film is located on the conductive layer and comprises a contact hole reaching the conductive layer. At least a surface part of the first insulating film is a BPSG film. The barrier metal covers an inner surface of the contact hole. The contact electrode is located in the contact hole and on the barrier metal. The surface electrode is located on the BPSG film and the contact electrode. The barrier metal is not interposed between the BPSG film and the surface electrode so that the surface electrode is directly in contact with the BPSG film. At least a part of the surface electrode is a bonding pad.

Abstract: A semiconductor device includes: a plurality of trenches provided in an upper surface of a semiconductor substrate; trench electrodes each provided in a corresponding one of the trenches; a first semiconductor layer of a first conductivity type provided in a first range interposed between adjacent ones of the trenches; a second semiconductor layer of a second conductivity type; a third semiconductor layer of the first conductivity type; an interlayer insulation film provided on the upper surface of the semiconductor substrate and including a plurality of contact holes; a first conductor layer provided in each of the contact holes; and a surface electrode provided on the interlayer insulation film and connected to each of the first conductor layers.

Abstract: An influence of a gate interference is suppressed and a reverse recovery property of a diode is improved. A diode includes a diode region located between the first boundary trench and the second boundary trench and a first and second IGBT regions. An emitter region and a body region are provided in each of the first and second IGBT regions. Each body region includes a body contact portion. An anode region is provided in the diode region. The anode region includes an anode contact portion. An interval between the first and second boundary trenches is equal to or longer than 200 ?m. An area ratio of the anode contact portion in the diode region is lower than each of an area ratio of the body contact portion in the first IGBT region and an area ratio of the body contact portion in the second IGBT region.

Abstract: A semiconductor device, in which, in a density distribution of first conductivity type impurities in the first conductivity type region measured along a thickness direction of the semiconductor substrate, a local maximum value N1, a local minimum value N2, a local maximum value N3, and a density N4 are formed in this order from front surface side, a relationship of N1>N3>N2>N4 is satisfied, a relationship of N3/10>N2 is satisfied, and a distance “a” from the surface to the depth having the local maximum value N1 is larger than twice a distance “b” from the depth having the local maximum value N1 to the depth having the local minimum N2.

Abstract: A semiconductor device comprises a conductive layer, a first insulating film, a barrier metal, a contact electrode, and a surface electrode. The first insulating film is located on the conductive layer and comprises a contact hole reaching the conductive layer. At least a surface part of the first insulating film is a BPSG film. The barrier metal covers an inner surface of the contact hole. The contact electrode is located in the contact hole and on the barrier metal. The surface electrode is located on the BPSG film and the contact electrode. The barrier metal is not interposed between the BPSG film and the surface electrode so that the surface electrode is directly in contact with the BPSG film. At least a part of the surface electrode is a bonding pad.

Abstract: In a semiconductor device including an IGBT and a diode, an upper-side lifetime control region, which is provided in the drift region within a range located above an intermediate depth of the drift region, is provided in a diode area and is not provided in an IGBT area. A first inter-trench semiconductor region, which is adjacent to a second inter-trench semiconductor region in a diode area, includes a barrier region of an n-type located between the body region and the drift region and a pillar region of the n-type extending from a position being in contact with the upper electrode to a position being in contact with the barrier region. Each of the second inter-trench semiconductor regions in the diode area does not include the pillar region.

Abstract: In a semiconductor device including an IGBT and a diode, an upper-side lifetime control region, which is provided in the drift region within a range located above an intermediate depth of the drift region, is provided in a diode area and is not provided in an IGBT area. A first inter-trench semiconductor region, which is adjacent to a second inter-trench semiconductor region in a diode area, includes a barrier region of an n-type located between the body region and the drift region and a pillar region of the n-type extending from a position being in contact with the upper electrode to a position being in contact with the barrier region. Each of the second inter-trench semiconductor regions in the diode area does not include the pillar region.

Abstract: A semiconductor device includes a semiconductor substrate that includes an IGBT region. A first lifetime control layer extending along a planar direction of the semiconductor substrate is provided in a range in a drift region that is closer to the rear surface than an intermediate portion of the semiconductor substrate in a thickness direction. A crystal defect density in the first lifetime control layer is higher than any of a crystal defect density in a region adjacent to the first lifetime control layer on the rear surface side and a crystal defect density in a region adjacent to the first lifetime control layer on a front surface side. A crystal defect density in a region between the first lifetime control layer and the rear surface is lower than a crystal defect density in a region between the first lifetime control layer and the front surface.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming of an interlayer insulating film on a semiconductor substrate; etching the interlayer insulating film to form a contact hole and an alignment hole wider than the contact hole; depositing a first metal layer having a thickness thicker than a half of the width of the contact hole and thinner than a half of the width of the alignment hole; etching the first metal layer so that a bottom surface of the alignment hole are exposed and the first metal layer remains covering a bottom surface of the contact hole; treating the semiconductor substrate based on the position of the alignment hole; and cutting a part of the semiconductor substrate including the alignment hole to divide a semiconductor device having the contact hole from the semiconductor substrate.

Abstract: A semiconductor device includes an interlayer insulating film in which first contact holes and second contact holes are provided. Each of the second contact holes has a width narrower than a width of the corresponding first contact hole. A contact plug is located in the corresponding second contact hole. An upper electrode layer is arranged on an upper surface of the interlayer insulating film, upper surfaces of the contact plugs, and inner surfaces of the first contact holes. The protective insulating film covers an upper surface of the external field. An end portion extending along a direction intersecting with the plurality of trenches of the protective insulating film extends through a range located above the plurality of the second contact holes. A pillar region is in contact with the upper electrode layer in the first contact hole.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming of an interlayer insulating film on a semiconductor substrate; etching the interlayer insulating film to form a contact hole and an alignment hole wider than the contact hole; depositing a first metal layer having a thickness thicker than a half of the width of the contact hole and thinner than a half of the width of the alignment hole; etching the first metal layer so that a bottom surface of the alignment hole are exposed and the first metal layer remains covering a bottom surface of the contact hole; treating the semiconductor substrate based on the position of the alignment hole; and cutting a part of the semiconductor substrate including the alignment hole to divide a semiconductor device having the contact hole from the semiconductor substrate.

Abstract: A semiconductor device, in which, in a density distribution of first conductivity type impurities in the first conductivity type region measured along a thickness direction of the semiconductor substrate, a local maximum value N1, a local minimum value N2, a local maximum value N3, and a density N4 are formed in this order from front surface side, a relationship of N1>N3>N2>N4 is satisfied, a relationship of N3/10>N2 is satisfied, and a distance “a” from the surface to the depth having the local maximum value N1 is larger than twice a distance “b” from the depth having the local maximum value N1 to the depth having the local minimum N2.

Abstract: A method of manufacturing an insulated gate switching device includes: forming a trench in a front surface of a semiconductor substrate; forming a gate insulating film in the trench; depositing an electrode layer made of semiconductor in the trench and on the front surface after forming the gate insulating film; polishing the electrode layer so as to remove a portion of the electrode layer on the front surface and expose an underlayer of the removed portion of the electrode layer; forming a cap insulating film in a surface layer of a portion of the electrode layer in the trench by heating the semiconductor substrate after exposing the underlayer; and implanting impurities from above the front surface into a range extending across the portion of the electrode layer in the trench and the semiconductor substrate.

Abstract: A small semiconductor device having a diode forward voltage less likely to change due to a gate potential is provided. An anode and an upper IGBT structure (emitter and body) are provided in a range in the substrate exposed at the upper surface. A trench, a gate insulating film, and a gate electrode extend along a border of the anode and the upper IGBT structure. Cathode and collector are provided in a range in the substrate exposed at the lower surface. A drift is provided between an upper structure and a lower structure. A crystal defect region extends across the drift above the cathode and the drift above the collector. When a thickness of the substrate is defined as x [?m] and a width of a portion of the crystal defect region that protrudes above the cathode is defined as y [?m], y?0.007x2?1.09x+126 is satisfied.

Abstract: An IGBT region includes a collector layer, a first drift layer, a first body layer, an emitter layer, and a trench gate reaching the first drift layer through the first body layer from a front surface side of a semiconductor substrate. A diode region includes a cathode layer, a second drift layer, and a second body layer. A lifetime control region which includes a peak of a crystal defect density is provided in the first drift layer and the second drift layer that are located between a depth of a lower end of the trench gate and surfaces of the first drift layer and the second drift layer. A silicon nitride film is further provided above the trench gate on the front surface side of the semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor substrate that includes an IGBT region. A first lifetime control layer extending along a planar direction of the semiconductor substrate is provided in a range in a drift region that is closer to the rear surface than an intermediate portion of the semiconductor substrate in a thickness direction. A crystal defect density in the first lifetime control layer is higher than any of a crystal defect density in a region adjacent to the first lifetime control layer on the rear surface side and a crystal defect density in a region adjacent to the first lifetime control layer on a front surface side. A crystal defect density in a region between the first lifetime control layer and the rear surface is lower than a crystal defect density in a region between the first lifetime control layer and the front surface.

Abstract: An electric device system includes a first unit and a second unit adjacent to each other. An elastically deformable first connecting terminal is provided in the first unit, and a second connecting terminal is provided in the second unit. When the first unit is assembled in the second unit, the first connecting terminal comes into contact with the second connecting terminal after sliding on an outer surface of a casing of the second unit. A bulging surface is provided in an exposed surface of the first connecting terminal, and a recess is provided in an exposed surface of the second connecting terminal. A part of the bulging surface and a part of an opening edge of the recess come into press-contact with each other by fitting a part of the bulging surface in the recess, thereby establishing electric conduction between the first connecting terminal and the second connecting terminal.

Abstract: A semiconductor device includes a first insulating film located on the semiconductor substrate and including a first contact hole; a contact plug located in the first contact hole; a first surface electrode extending on the first insulating film and the contact plug; a conductive layer; a second insulating film located on the conductive layer and including a second contact hole wider than the first contact hole; a side metal layer covering a corner portion in the second contact hole and configured of a same kind of metal as the contact plug; and a second surface electrode extending on the second insulating film and in the second contact hole, covering the side metal layer, and configured of a different kind of metal from the contact plug. A bonding pad is located in a part of the second surface electrode on the bottom surface of the second contact hole.