Patents by Inventor Shinya Iwasaki

Shinya Iwasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160163647
    Abstract: A semiconductor device comprises a conductive layer, a first insulating film, a barrier metal, a contact electrode, and a surface electrode. The first insulating film is located on the conductive layer and comprises a contact hole reaching the conductive layer. At least a surface part of the first insulating film is a BPSG film. The barrier metal covers an inner surface of the contact hole. The contact electrode is located in the contact hole and on the barrier metal. The surface electrode is located on the BPSG film and the contact electrode. The barrier metal is not interposed between the BPSG film and the surface electrode so that the surface electrode is directly in contact with the BPSG film. At least a part of the surface electrode is a bonding pad.
    Type: Application
    Filed: November 20, 2015
    Publication date: June 9, 2016
    Inventors: Shinya IWASAKI, Satoru KAMEYAMA
  • Patent number: 9337058
    Abstract: There is provided a method for reducing the nonuniformity of forward voltage Vf of an N-type semiconductor wafer in which density of impurities included in an N-layer is nonuniformly distributed in a plane view of the semiconductor wafer. The method reduces the nonuniformity of forward voltage, by irradiating charged particles to the N-type semiconductor wafer, and generating defects in the N-layer to reduce the nonuniformity of forward voltage. In one aspect of the method, charged particles are irradiated so that a reaching positon in a depth direction or an irradiation density may differ according to the density of impurities in the N-layer in the plane view of the semiconductor wafer.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: May 10, 2016
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Shinya Iwasaki
  • Publication number: 20160027881
    Abstract: Disclosed herein is a semiconductor device which includes a semiconductor substrate and a trench gate. The semiconductor substrate includes a drift layer, a body layer, and a first semiconductor layer provided on a part of a front surface of the body layer. The trench gate extends from a front surface of the semiconductor substrate to reach the drift layer. The trench gate includes a gate insulating film and a gate electrode. The inner wall of the trench, which is located at a depth where the inner wall makes contact with the body layer, is a crystal plane. A width of the trench in a transverse direction includes a width located at the front surface of the semiconductor substrate that is narrower than a width located at a depth from a lower end of the first semiconductor layer to a lower end of the body layer.
    Type: Application
    Filed: March 15, 2013
    Publication date: January 28, 2016
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Shinya IWASAKI
  • Publication number: 20160005622
    Abstract: There is provided a method for reducing the nonuniformity of forward voltage Vf of an N-type semiconductor wafer in which density of impurities included in an N-layer is nonuniformly distributed in a plane view of the semiconductor wafer. The method reduces the nonuniformity of forward voltage, by irradiating charged particles to the N-type semiconductor wafer, and generating defects in the N-layer to reduce the nonuniformity of forward voltage. In one aspect of the method, charged particles are irradiated so that a reaching positon in a depth direction or an irradiation density may differ according to the density of impurities in the N-layer in the plane view of the semiconductor wafer.
    Type: Application
    Filed: March 6, 2013
    Publication date: January 7, 2016
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Shinya IWASAKI
  • Patent number: 9136614
    Abstract: A conductor connection tool includes a terminal platform base, a conduction fitting accommodated in a fitting recessed part of the terminal platform base. The conduction fitting is formed in a substantially U shape and includes a bottom plate portion, a vertical portion bent vertically upward from one end of the bottom plate portion, and an attachment portion extending from an upper end of the vertical portion in parallel to the bottom plate portion, and having a terminal portion extending in the opposite direction to the attachment portion. A plate spring bent in a substantially V shape with one side serving as an attachment piece to be fixed to the attachment portion of the conduction fitting with the other side serving as a locking piece whose front end is to be brought into pressure contact with the bottom plate portion of the conduction fitting.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: September 15, 2015
    Assignee: OMRON Corporation
    Inventors: Naoya Sasano, Makoto Sato, Motoyuki Tomizu, Jun Yamane, Shinya Iwasaki, Naoki Ueno
  • Patent number: 8846544
    Abstract: A semiconductor device comprises a semiconductor substrate, a first electrode formed on a first main surface of the semiconductor substrate, and a second electrode formed on a second main surface of the semiconductor substrate. The semiconductor substrate includes a first region in which a density of oxygen-vacancy defects is greater than a density of vacancy cluster defects, and a second region in which the density of vacancy cluster defects is greater than the density of oxygen-vacancy defects.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: September 30, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Tadashi Misumi, Shinya Iwasaki, Takahide Sugiyama
  • Patent number: 8829055
    Abstract: A drug and a composition for inhibiting biofilm formation are provided. A biofilm formation inhibitor composition containing the following component (A): (A) at least one or more selected from compounds represented by Formula (1) to Formula (4): wherein R1 to R5 each represent an alkyl group or the like; EO represents an ethyleneoxy group; p represents an integer from 0 to 5; and m+n represents a number from 0 to 30, or a salt thereof; and (B) a surfactant.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: September 9, 2014
    Assignee: Kao Corporation
    Inventors: Tetsuya Okano, Shinya Iwasaki, Kazuo Isobe, Eiko Ishizuka
  • Publication number: 20140179116
    Abstract: A semiconductor device comprises a semiconductor substrate, a first electrode formed on a first main surface of the semiconductor substrate, and a second electrode formed on a second main surface of the semiconductor substrate. The semiconductor substrate includes a first region in which a density of oxygen-vacancy defects is greater than a density of vacancy cluster defects, and a second region in which the density of vacancy cluster defects is greater than the density of oxygen-vacancy defects.
    Type: Application
    Filed: February 28, 2014
    Publication date: June 26, 2014
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: TADASHI MISUMI, SHINYA IWASAKI, TAKAHIDE SUGIYAMA
  • Patent number: 8742454
    Abstract: In a semiconductor device having a semiconductor substrate on which a diode and an IGBT are formed, a cathode region of the diode and a collector region of the IGBT are formed in a range exposed to one surface of the semiconductor substrate. On the surface, a first conductor layer that is in contact with the cathode region, and a second conductor layer that is in contact with the collector region are formed. The work function of the second conductor layer is larger than the work function of the first conductor layer.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: June 3, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Shinya Iwasaki
  • Patent number: 8698285
    Abstract: A semiconductor device comprises a semiconductor substrate, a first electrode formed on a first main surface of the semiconductor substrate, and a second electrode formed on a second main surface of the semiconductor substrate. The semiconductor substrate includes a first region in which a density of oxygen-vacancy defects is greater than a density of vacancy cluster defects, and a second region in which the density of vacancy cluster defects is greater than the density of oxygen-vacancy defects.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: April 15, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Tadashi Misumi, Shinya Iwasaki, Takahide Sugiyama
  • Patent number: 8686467
    Abstract: A semiconductor device includes a semiconductor substrate in which a diode region and an IGBT region are formed, wherein a lower surface side of the semiconductor substrate comprises a low impurity region provided between a second conductivity type cathode region of the diode region and a first conductivity type collector region of the IGBT region. The low impurity region includes at least one of a first conductivity type first low impurity region which has a lower density of first conductivity type impurities than that in the collector region and a second conductivity type second low impurity region which has a lower density of second conductivity type impurities than that in the cathode region.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: April 1, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Shinya Iwasaki, Akitaka Soeno
  • Publication number: 20140017930
    Abstract: A conductor connection tool includes a terminal platform base, a conduction fitting accommodated in a fitting recessed part of the terminal platform base. The conduction fitting is formed in a substantially U shape and includes a bottom plate portion, a vertical portion bent vertically upward from one end of the bottom plate portion, and an attachment portion extending from an upper end of the vertical portion in parallel to the bottom plate portion, and having a terminal portion extending in the opposite direction to the attachment portion. A plate spring bent in a substantially V shape with one side serving as an attachment piece to be fixed to the attachment portion of the conduction fitting with the other side serving as a locking piece whose front end is to be brought into pressure contact with the bottom plate portion of the conduction fitting.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 16, 2014
    Applicant: OMRON CORPORATION
    Inventors: NAOYA SASANO, Makoto Sato, Motoyuki Tomizu, Jun Yamane, Shinya Iwasaki, Naoki Ueno
  • Patent number: 8514240
    Abstract: A processing unit executes a process for creating a dedicated color palette (color palette dedicated for a palm vein GUI) as an initialization process, and creates the color palette dedicated for a palm vein GUI. The processing unit replaces a 256-level gradation grayscale palette set in an acquired photographed image with the color palette dedicated for the palm vein GUI. The processing unit performs guide GUI display for guiding a palm to an appropriate position, using a display image formed by setting the color palette dedicated for the palm vein GUI for the photographed image acquired from a photographed image-acquiring process.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: August 20, 2013
    Assignee: Fujitsu Frontech Limited
    Inventors: Naoko Suzuki, Junichiro Toya, Shinya Iwasaki, Yasuhiko Mita, Kiyomi Ozawa
  • Publication number: 20130181254
    Abstract: In a semiconductor device having a semiconductor substrate on which a diode and an IGBT are formed, a cathode region of the diode and a collector region of the IGBT are formed in a range exposed to one surface of the semiconductor substrate. On the surface, a first conductor layer that is in contact with the cathode region, and a second conductor layer that is in contact with the collector region are formed. The work function of the second conductor layer is larger than the work function of the first conductor layer.
    Type: Application
    Filed: January 10, 2013
    Publication date: July 18, 2013
    Inventor: Shinya IWASAKI
  • Patent number: 8423786
    Abstract: A biometrics authentication device which detects body characteristics, performs verification against registered biometrics data, and performs individual authentication, by which confidentiality is improved even when biometrics data is separated, distributed and stored. A biometrics information key is created from biometrics data detected by a detection device, the biometrics data is divided into a plurality of portions, and the portions are stored on different media. The biometrics information key is stored on one media, and at the time of authentication, the separated biometrics data portions are combined and a biometrics information key is created and is compared with the biometrics information key, to judge the linked relationship. Hence confidentiality of the association of the individual separated data portions can be improved even when the biometrics data is separated, distributed and stored, contributing to prevent illicit use resulting from leakage or theft of biometrics data.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: April 16, 2013
    Assignees: Fujitsu Limited, Fujitsu Frontech Limited
    Inventors: Kazuo Takaku, Yasuhiko Mita, Naoko Suzuki, Shinya Iwasaki, Masayuki Yano, Ikuo Mutou
  • Publication number: 20130001639
    Abstract: A semiconductor device includes a semiconductor substrate in which a diode region and an IGBT region are formed, wherein a lower surface side of the semiconductor substrate comprises a low impurity region provided between a second conductivity type cathode region of the diode region and a first conductivity type collector region of the IGBT region. The low impurity region includes at least one of a first conductivity type first low impurity region which has a lower density of first conductivity type impurities than that in the collector region and a second conductivity type second low impurity region which has a lower density of second conductivity type impurities than that in the cathode region.
    Type: Application
    Filed: September 11, 2012
    Publication date: January 3, 2013
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shinya IWASAKI, Akitaka SOENO
  • Patent number: 8334193
    Abstract: Provided is a method of manufacturing a semiconductor device capable of preventing a relative displacement of the positions between a range where impurity ions are injected and a range where charged particles are injected. The method of manufacturing the semiconductor device includes: irradiating impurity ions in a state in which a mask is disposed between an impurity ion irradiation apparatus and a semiconductor substrate; and irradiating charged particles to form a short carrier lifetime region, in a state in which the mask is disposed between a charged particle irradiation apparatus and the semiconductor substrate. A relative positional relationship between the mask and the semiconductor substrate is not changed from a beginning of one of the irradiating the impurity ions and the irradiating the charged particles to a completion of both of the irradiating the impurity ions and the irradiating the charged particles.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: December 18, 2012
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Shinya Iwasaki, Akira Kamei
  • Publication number: 20120299949
    Abstract: A processing unit executes a process for creating a dedicated color palette (color palette dedicated for a palm vein GUI) as an initialization process, and creates the color palette dedicated for a palm vein GUI. The processing unit replaces a 256-level gradation grayscale palette set in an acquired photographed image with the color palette dedicated for the palm vein GUI. The processing unit performs guide GUI display for guiding a palm to an appropriate position, using a display image formed by setting the color palette dedicated for the palm vein GUI for the photographed image acquired from a photographed image-acquiring process.
    Type: Application
    Filed: August 7, 2012
    Publication date: November 29, 2012
    Applicant: FUJITSU FRONTECH LIMITED
    Inventors: Naoko Suzuki, Junichiro Toya, Shinya Iwasaki, Yasuhiko Mita, Kiyomi Ozawa
  • Patent number: 8184866
    Abstract: A biometrics authentication device identifies characteristics of the body from captured images of the body and performs individual authentication. The device guides a user, at the time of verification, to the image capture state at the time of registration of biometrics characteristic data. At the time of registration of biometrics characteristic data, body image capture state data is extracted from an image captured by an image capture unit and is registered in a storage unit, and at the time of verification the registered image capture state data is read from the storage unit and is compared with image capture state data extracted at the time of verification, and guidance of the body is provided. Alternatively, an outline of the body at the time of registration, taken from image capture state data at the time of registration, is displayed.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: May 22, 2012
    Assignees: Fujitsu Limited, Fujitsu Frontech Limited
    Inventors: Kazuo Takaku, Yasuhiko Mita, Naoko Suzuki, Shinya Iwasaki, Masayuki Yano
  • Publication number: 20120015508
    Abstract: Provided is a method of manufacturing a semiconductor device capable of preventing a relative displacement of the positions between a range where impurity ions are injected and a range where charged particles are injected. The method of manufacturing the semiconductor device includes: irradiating impurity ions in a state in which a mask is disposed between an impurity ion irradiation apparatus and a semiconductor substrate; and irradiating charged particles to form a short carrier lifetime region, in a state in which the mask is disposed between a charged particle irradiation apparatus and the semiconductor substrate. A relative positional relationship between the mask and the semiconductor substrate is not changed from a beginning of one of the irradiating the impurity ions and the irradiating the charged particles to a completion of both of the irradiating the impurity ions and the irradiating the charged particles.
    Type: Application
    Filed: September 23, 2011
    Publication date: January 19, 2012
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shinya IWASAKI, Akira KAMEI