Patents by Inventor Shinya Naito

Shinya Naito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200365957
    Abstract: A temperature detector detects a temperature of an electricity storage unit installed in a casing. A controller estimates a temperature outside the casing on the basis of a detection temperature of the electricity storage unit detected by the temperature detector. The controller estimates an outdoor air temperature outside the casing on the basis of a change amount of detection temperature per a predetermined period detected in a state where a cooling unit is operated and a change amount of detection temperature per the predetermined period detected in a state where the cooling unit is stopped.
    Type: Application
    Filed: May 16, 2017
    Publication date: November 19, 2020
    Applicant: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Shinya Nishikawa, Takashi Hasegawa, Keisuke Naito
  • Patent number: 10827658
    Abstract: An electronic device housing of the present invention is a housing for internally accommodating an electronic device and is provided with a metal bottom plate, and metal side plates folded and integrally connected to the bottom plate, in which, in a metal member (M) formed of at least the bottom plate and the side plate, a thermoplastic resin member is joined to a portion of the surface of the plate-shaped metal member (M), the metal member (M) is reinforced by a thermoplastic resin member, and the thermoplastic resin member is joined to both surfaces of the plate-shaped metal member (M).
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: November 3, 2020
    Assignee: MITSUI CHEMICALS, INC.
    Inventors: Shinya Naito, Nobuyoshi Shimbori
  • Publication number: 20200294554
    Abstract: A semiconductor memory device according to an embodiment includes a substrate, first and second conductive layers, and a first pillar. The first conductive layer is provided above the substrate and includes a first N-type semiconductor region and a first P-type semiconductor region. The second conductive layers are provided above the first conductive layer and stacked at intervals. The first pillar includes a first semiconductor layer and a first insulating layer. The first semiconductor layer is provided through the second conductive layers and is in contact with each of the first N-type semiconductor region and the first P-type semiconductor region. The first insulating layer is provided between the first semiconductor layer and the second conductive layers.
    Type: Application
    Filed: August 30, 2019
    Publication date: September 17, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Takayuki KAKEGAWA, Shinya NAITO, Masaki KONDO, Takashi KURUSU, Hiroshi TAKEDA, Nayuta KARIYA
  • Publication number: 20200122971
    Abstract: A suspension body for an elevator includes a core having a belt-like shape, and a covering layer covering at least a part of an outer periphery of the core. The core includes a load bearing layer. The load bearing layer is formed of an impregnation resin and a plurality of high-strength fibers. Further, the load bearing layer is divided into a plurality of segment layers arranged apart from each other in a thickness direction of the core. An intermediate layer made of a material different from that for the load bearing layer is interposed between the segment layers adjacent to each other in the thickness direction of the core.
    Type: Application
    Filed: April 26, 2018
    Publication date: April 23, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Masahiko HIDA, Michihito MATSUMOTO, Haruhiko KAKUTANI, Rikio KONDO, Shinya NAITO, Naoya TANAKA, Masaya SERA
  • Patent number: 10559361
    Abstract: According to one embodiment, there is provided a semiconductor device including a first semiconductor region, a stacked body, a semiconductor channel, a gate insulating film, and a control circuit. The stacked body is of conductive films arranged in a stacking direction with an insulator interposed. The semiconductor channel penetrates the stacked body in the stacking direction, and is electrically connected at one end to the first semiconductor region. The gate insulating film is arranged between the stacked body and the semiconductor channel. The control circuit supplies a first voltage to a closest conductive film of the stacked body to the first semiconductor region, and supplies a second voltage higher than the first voltage to the first semiconductor region, at a time of reading information from one of memory cells formed at positions where the conductive films intersect with the semiconductor channel.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: February 11, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Shinya Naito, Takayuki Kakegawa
  • Publication number: 20190285502
    Abstract: A dynamic balancing test and correction apparatus capable of shortening the time required for correcting imbalance in a correction part and improving the entire workflow of the apparatus.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 19, 2019
    Applicant: Shimadzu Industrial Systems Co., Ltd.
    Inventors: Atsushi KAJIKAWA, Shinya NAITO
  • Publication number: 20190287628
    Abstract: According to one embodiment, there is provided a semiconductor device including a first semiconductor region, a stacked body, a semiconductor channel, a gate insulating film, and a control circuit. The stacked body is of conductive films arranged in a stacking direction with an insulator interposed. The semiconductor channel penetrates the stacked body in the stacking direction, and is electrically connected at one end to the first semiconductor region. The gate insulating film is arranged between the stacked body and the semiconductor channel. The control circuit supplies a first voltage to a closest conductive film of the stacked body to the first semiconductor region, and supplies a second voltage higher than the first voltage to the first semiconductor region, at a time of reading information from one of memory cells formed at positions where the conductive films intersect with the semiconductor channel.
    Type: Application
    Filed: September 10, 2018
    Publication date: September 19, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Shinya NAITO, Takayuki KAKEGAWA
  • Patent number: 10332905
    Abstract: A semiconductor memory device includes a conductive layer; a plurality of electrode layers stacked on the conductive layer; a semiconductor pillar extending through the electrode layers in a stacking direction and electrically connected to the conductive layer; and an insulating layer positioned between the semiconductor pillar and the electrode layers and extending along the semiconductor pillar. The semiconductor pillar has a channel portion extending through the electrode layers and a high impurity concentration portion positioned at a bottom end on a side of the conductive layer. The high impurity concentration portion includes an impurity of a higher concentration than an impurity concentration in the channel portion. The insulating layer has an end portion extending toward a center of the bottom end of the semiconductor pillar, and a boundary of the channel portion and the high impurity concentration portion is positioned above the end portion of the insulating layer.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: June 25, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinya Naito, Osamu Fujii, Takayuki Kakegawa
  • Publication number: 20190191598
    Abstract: An electronic device housing of the present invention is a housing for internally accommodating an electronic device and is provided with a metal bottom plate, and metal side plates folded and integrally connected to the bottom plate, in which, in a metal member (M) formed of at least the bottom plate and the side plate, a thermoplastic resin member is joined to a portion of the surface of the plate-shaped metal member (M), the metal member (M) is reinforced by a thermoplastic resin member, and the thermoplastic resin member is joined to both surfaces of the plate-shaped metal member (M).
    Type: Application
    Filed: August 23, 2017
    Publication date: June 20, 2019
    Applicant: MITSUI CHEMICALS, INC.
    Inventors: Shinya NAITO, Nobuyoshi SHIMBORI
  • Patent number: 10283522
    Abstract: According to an embodiment, a semiconductor memory device includes a stacked body in which insulating layers and electrode films are alternately stacked, a pillar member arranged in a memory hole that is disposed in the stacked body in a thickness direction, and a semiconductor layer provided below the pillar member. The pillar member has a structure in which a memory film and a channel layer are stacked in order from a side of the stacked body. The channel layer has a stacked structure that includes an outer channel semiconductor layer, an intermediate layer made of an insulating material, and an inner channel semiconductor layer, from a side of the memory film. Both of the outer channel semiconductor layer and the inner channel semiconductor layer are electrically connected to the semiconductor layer.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: May 7, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tomofumi Zushi, Shinya Naito
  • Patent number: 10276590
    Abstract: According to one embodiment, a semiconductor device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed; a semiconductor body provided in the stacked body; and an insulating film. The semiconductor body includes a channel portion extending in a stacking direction of the stacked body, and a lower end portion of the semiconductor body provided between the channel portion and the substrate. The insulating film includes a charge storage film provided between the stacked body and the semiconductor body. A lower end portion of the insulating film surrounds the lower end portion of the semiconductor body. An upper surface of the lower end portion of the insulating film is provided at a lower height than an upper surface of the lower end portion of the semiconductor body in the stacking direction.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: April 30, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsufumi Hamada, Hikari Tajima, Takashi Izumida, Nobutoshi Aoki, Shinya Naito, Takayuki Kakegawa, Takaya Yamanaka
  • Publication number: 20180277560
    Abstract: According to an embodiment, a semiconductor memory device includes a stacked body in which insulating layers and electrode films are alternately stacked, a pillar member arranged in a memory hole that is disposed in the stacked body in a thickness direction, and a semiconductor layer provided below the pillar member. The pillar member has a structure in which a memory film and a channel layer are stacked in order from a side of the stacked body. The channel layer has a stacked structure that includes an outer channel semiconductor layer, an intermediate layer made of an insulating material, and an inner channel semiconductor layer, from a side of the memory film. Both of the outer channel semiconductor layer and the inner channel semiconductor layer are electrically connected to the semiconductor layer.
    Type: Application
    Filed: September 6, 2017
    Publication date: September 27, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Tomofumi Zushi, Shinya Naito
  • Publication number: 20180175056
    Abstract: According to one embodiment, a semiconductor device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed; a semiconductor body provided in the stacked body; and an insulating film. The semiconductor body includes a channel portion extending in a stacking direction of the stacked body, and a lower end portion of the semiconductor body provided between the channel portion and the substrate. The insulating film includes a charge storage film provided between the stacked body and the semiconductor body. A lower end portion of the insulating film surrounds the lower end portion of the semiconductor body. An upper surface of the lower end portion of the insulating film is provided at a lower height than an upper surface of the lower end portion of the semiconductor body in the stacking direction.
    Type: Application
    Filed: February 14, 2018
    Publication date: June 21, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsufumi HAMADA, Hikari TAJIMA, Takashi IZUMIDA, Nobutoshi AOKI, Shinya NAITO, Takayuki KAKEGAWA, Takaya YAMANAKA
  • Patent number: 9991272
    Abstract: According to one embodiment, a semiconductor memory device includes a base semiconductor layer, first and second conductive layers, a semiconductor body, a memory layer, first and second semiconductor regions, and an insulating portion. The first conductive layer is separated from the base semiconductor layer in a first direction. The second conductive layer is provided between the base semiconductor layer and the first conductive layer. The semiconductor body extends through the first conductive layer in the first direction. The memory layer is provided between the semiconductor body and the first conductive layer. The first semiconductor region is provided between the memory layer and the base semiconductor layer and between the semiconductor body and the base semiconductor layer, and is of a first conductivity type. The second semiconductor region is provided between the first semiconductor region and the memory layer, and is of a second conductivity type.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: June 5, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsufumi Hamada, Shinya Naito, Hiroshi Kanno, Yoshiaki Fukuzumi
  • Publication number: 20180083102
    Abstract: A semiconductor memory device includes a conductive layer; a plurality of electrode layers stacked on the conductive layer; a semiconductor pillar extending through the electrode layers in a stacking direction and electrically connected to the conductive layer; and an insulating layer positioned between the semiconductor pillar and the electrode layers and extending along the semiconductor pillar. The semiconductor pillar has a channel portion extending through the electrode layers and a high impurity concentration portion positioned at a bottom end on a side of the conductive layer. The high impurity concentration portion includes an impurity of a higher concentration than an impurity concentration in the channel portion. The insulating layer has an end portion extending toward a center of the bottom end of the semiconductor pillar, and a boundary of the channel portion and the high impurity concentration portion is positioned above the end portion of the insulating layer.
    Type: Application
    Filed: March 16, 2017
    Publication date: March 22, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Shinya NAITO, Osamu FUJII, Takayuki KAKEGAWA
  • Publication number: 20180076210
    Abstract: According to one embodiment, a semiconductor memory device includes a base semiconductor layer, first and second conductive layers, a semiconductor body, a memory layer, first and second semiconductor regions, and an insulating portion. The first conductive layer is separated from the base semiconductor layer in a first direction. The second conductive layer is provided between the base semiconductor layer and the first conductive layer. The semiconductor body extends through the first conductive layer in the first direction. The memory layer is provided between the semiconductor body and the first conductive layer. The first semiconductor region is provided between the memory layer and the base semiconductor layer and between the semiconductor body and the base semiconductor layer, and is of a first conductivity type. The second semiconductor region is provided between the first semiconductor region and the memory layer, and is of a second conductivity type.
    Type: Application
    Filed: March 16, 2017
    Publication date: March 15, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Tatsufumi HAMADA, Shinya NAITO, Hiroshi KANNO, Yoshiaki FUKUZUMI
  • Patent number: 9917099
    Abstract: According to one embodiment, a semiconductor device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed; a semiconductor body provided in the stacked body; and an insulating film. The semiconductor body includes a channel portion extending in a stacking direction of the stacked body, and a lower end portion of the semiconductor body provided between the channel portion and the substrate. The insulating film includes a charge storage film provided between the stacked body and the semiconductor body. A lower end portion of the insulating film surrounds the lower end portion of the semiconductor body. An upper surface of the lower end portion of the insulating film is provided at a lower height than an upper surface of the lower end portion of the semiconductor body in the stacking direction.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: March 13, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsufumi Hamada, Hikari Tajima, Takashi Izumida, Nobutoshi Aoki, Shinya Naito, Takayuki Kakegawa, Takaya Yamanaka
  • Patent number: 9909950
    Abstract: An inspection method and an inspection apparatus capable of readily determining the necessity of replacement of a resin shock absorber at an elevator inspection location without using a car of a rated weight. First, an indenter is pressed into a resin shock absorber for an elevator. A load of pressing the indenter into the resin shock absorber is released. A physical property value indicative of a repulsive force that causes the indenter to bounce from the resin shock absorber by releasing the load is measured. The necessity of replacement of the resin shock absorber is determined by comparing a result of the physical property value obtained by measuring the repulsive force with a reference value prepared in advance.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: March 6, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinya Naito, Hisashi Furuzawa, Michio Murai
  • Publication number: 20170271262
    Abstract: According to one embodiment, a substrate includes a first portion and a second portion. The first portion has a columnar configuration. The second portion has an upper surface continuous with a side surface of the first portion via a corner. A plurality of electrode layers include a lowermost electrode layer opposing the side surface of the first portion above the second portion. An insulating film is provided between the side surface of the first portion and a side surface of the lowermost electrode layer, and between the upper surface of the second portion and a lower surface of the lowermost electrode layer. An angle formed between the upper surface of the second portion and the corner of the substrate on the insulating film side is greater than 90°.
    Type: Application
    Filed: July 14, 2016
    Publication date: September 21, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shinya NAITO, Takayuki Kakegawa
  • Patent number: 9768117
    Abstract: According to one embodiment, a substrate includes a first portion and a second portion. The first portion has a columnar configuration. The second portion has an upper surface continuous with a side surface of the first portion via a corner. A plurality of electrode layers include a lowermost electrode layer opposing the side surface of the first portion above the second portion. An insulating film is provided between the side surface of the first portion and a side surface of the lowermost electrode layer, and between the upper surface of the second portion and a lower surface of the lowermost electrode layer. An angle formed between the upper surface of the second portion and the corner of the substrate on the insulating film side is greater than 90°.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: September 19, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinya Naito, Takayuki Kakegawa