Patents by Inventor Shinya Sasagawa

Shinya Sasagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160240684
    Abstract: A miniaturized transistor, a transistor with low parasitic capacitance, a transistor with high frequency characteristics, or a semiconductor device including the transistor is provided. The semiconductor device includes a first insulator, an oxide semiconductor over the first insulator, a first conductor and a second conductor that are in contact with the oxide semiconductor, a second insulator that is over the first and second conductors and has an opening reaching the oxide semiconductor, a third insulator over the oxide semiconductor and the second insulator, and a fourth conductor over the third insulator. The first conductor includes a first region and a second region. The second conductor includes a third region and a fourth region. The second region faces the third region with the first conductor and the first insulator interposed therebetween. The second region is thinner than the first region. The third region is thinner than the fourth region.
    Type: Application
    Filed: February 9, 2016
    Publication date: August 18, 2016
    Inventors: Shunpei YAMAZAKI, Yoshinobu ASAMI, Yutaka OKAZAKI, Motomu KURATA, Katsuaki TOCHIBAYASHI, Shinya SASAGAWA, Kensuke YOSHIZUMI, Hideomi SUZAWA
  • Patent number: 9419018
    Abstract: A semiconductor device that occupies a small area and has a high degree of integration is provided. The semiconductor device includes a first insulating layer, a conductive layer, and a second insulating layer. The conductive layer is between the first insulating layer and the second insulating layer. The first insulating layer, the conductive layer, and the second insulating layer overlap with each other in a region. A contact plug penetrates the first insulating layer, the conductive layer, and the second insulating layer. In a depth direction from the second insulating layer to the first insulating layer, a diameter of the contact plug changes to a smaller value at an interface between the second insulating layer and the conductive layer.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: August 16, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Hidekazu Miyairi, Shunpei Yamazaki, Motomu Kurata
  • Patent number: 9419145
    Abstract: To give favorable electrical characteristics to a semiconductor device. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a pair of electrodes over the semiconductor layer and each electrically connected to the semiconductor layer, a gate electrode over the semiconductor layer, and a gate insulating layer between the semiconductor layer and the gate electrode. The insulating layer includes an island-shaped projecting portion. A top surface of the projecting portion of the insulating layer is in contact with a bottom surface of the semiconductor layer, and is positioned on an inner side of the semiconductor layer when seen from above. The pair of electrodes covers part of a top surface and part of side surfaces of the semiconductor layer. Furthermore, the gate electrode and the gate insulating layer cover side surfaces of the projecting portion of the insulating layer.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: August 16, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Motomu Kurata
  • Publication number: 20160218219
    Abstract: A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.
    Type: Application
    Filed: January 14, 2016
    Publication date: July 28, 2016
    Inventors: Yoshinobu ASAMI, Yutaka OKAZAKI, Satoru OKAMOTO, Shinya SASAGAWA
  • Publication number: 20160190347
    Abstract: A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a source electrode layer and a drain electrode layer electrically connected to the semiconductor layer, a gate insulating film over the semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer overlapping with part of the semiconductor layer, part of the source electrode layer, and part of the drain electrode layer with the gate insulating film therebetween. A cross section of the semiconductor layer in the channel width direction is substantially triangular or substantially trapezoidal. The effective channel width is shorter than that for a rectangular cross section.
    Type: Application
    Filed: March 7, 2016
    Publication date: June 30, 2016
    Inventors: Shinya SASAGAWA, Motomu KURATA, Kazuya HANAOKA, Yoshiyuki KOBAYASHI, Daisuke MATSUBAYASHI
  • Patent number: 9379136
    Abstract: When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: June 28, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Hitoshi Nakayama, Masashi Tsubuku, Daigo Shimada
  • Patent number: 9373708
    Abstract: To establish a processing technique in manufacture of a semiconductor device including an In—Sn—Zn—O-based semiconductor. An In—Sn—Zn—O-based semiconductor layer is selectively etched by dry etching with the use of a gas containing chlorine such as Cl2, BCl3, SiCl4, or the like. In formation of a source electrode layer and a drain electrode layer, a conductive layer on and in contact with the In—Sn—Zn—O-based semiconductor layer can be selectively etched with little removal of the In—Sn—Zn—O-based semiconductor layer with the use of a gas containing oxygen or fluorine in addition to a gas containing chlorine.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: June 21, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shinya Sasagawa, Hitoshi Nakayama, Hiroshi Fujiki
  • Patent number: 9373525
    Abstract: An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: June 21, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Shinya Sasagawa, Taiga Muraoka
  • Patent number: 9368636
    Abstract: A substrate having an insulating surface is prepared; a stacked film including a first oxide semiconductor layer and a second oxide semiconductor layer is formed over the substrate; a mask layer is formed over part of the stacked film and then dry etching treatment is performed, so that the stacked film is removed, with a region provided with the mask layer remaining, and a reaction product is formed on a side surface of the remaining stacked film; the reaction product is removed by wet etching treatment after removal of the mask layer; a source electrode and a drain electrode are formed over the stacked film; and a third oxide semiconductor layer, a gate insulating film, and a gate electrode are stacked and formed in this order over the stacked film, and the source electrode and the drain electrode.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: June 14, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Motomu Kurata, Shinya Sasagawa, Taiga Muraoka, Hiroaki Honda, Takashi Hamada
  • Publication number: 20160163744
    Abstract: A semiconductor device in which an increase in oxygen vacancies in an oxide semiconductor layer can be suppressed is provided. A semiconductor device with favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. A semiconductor device includes an oxide semiconductor layer in a channel formation region, and by the use of an oxide insulating film below and in contact with the oxide semiconductor layer and a gate insulating film over and in contact with the oxide semiconductor layer, oxygen of the oxide insulating film or the gate insulating film is supplied to the oxide semiconductor layer. Further, a conductive nitride is used for metal films of a source electrode layer, a drain electrode layer, and a gate electrode layer, whereby diffusion of oxygen to the metal films is suppressed.
    Type: Application
    Filed: February 11, 2016
    Publication date: June 9, 2016
    Inventors: Shunpei YAMAZAKI, Hideomi SUZAWA, Shinya SASAGAWA, Tetsuhiro TANAKA
  • Publication number: 20160126360
    Abstract: A miniaturized transistor having excellent electrical characteristics is provided with high yield. Further, a semiconductor device including the transistor and having high performance and high reliability is manufactured with high productivity. In a semiconductor device including a transistor in which an oxide semiconductor film including a channel formation region and low-resistance regions between which the channel formation region is sandwiched, a gate insulating film, and a gate electrode layer whose top surface and side surface are covered with an insulating film including an aluminum oxide film are stacked, a source electrode layer and a drain electrode layer are in contact with part of the oxide semiconductor film and the top surface and a side surface of the insulating film including an aluminum oxide film.
    Type: Application
    Filed: January 11, 2016
    Publication date: May 5, 2016
    Inventors: Shinya SASAGAWA, Motomu KURATA
  • Patent number: 9330909
    Abstract: A semiconductor device in which an increase in oxygen vacancies in an oxide semiconductor layer can be suppressed is provided. A semiconductor device with favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. A semiconductor device includes an oxide semiconductor layer in a channel formation region, and by the use of an oxide insulating film below and in contact with the oxide semiconductor layer and a gate insulating film over and in contact with the oxide semiconductor layer, oxygen of the oxide insulating film or the gate insulating film is supplied to the oxide semiconductor layer. Further, a conductive nitride is used for a metal film of a source electrode layer and a drain electrode layer, whereby diffusion of oxygen to the metal film is suppressed.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: May 3, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Shinya Sasagawa, Tetsuhiro Tanaka
  • Publication number: 20160099259
    Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.
    Type: Application
    Filed: September 30, 2015
    Publication date: April 7, 2016
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Okazaki, Tomoaki MORIWAKA, Shinya SASAGAWA, Takashi OHTSUKI
  • Patent number: 9305774
    Abstract: A stable and minute processing method of a thin film is provided. Further, a miniaturized semiconductor device is provided. A method for processing a thin film includes the following steps: forming a film to be processed over a formation surface; forming an organic coating film over the film to be processed; forming a resist film over the organic coating film; exposing the resist film to light or an electron beam; removing part of the resist film by development to expose part of the organic coating film; depositing an organic material layer on the top surface and a side surface of the resist film by plasma treatment; etching part of the organic coating film using the resist film and the organic material layer as masks to expose part of the film to be processed; and etching part of the film to be processed using the resist film and the organic material layer as masks.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: April 5, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Taiga Muraoka, Motomu Kurata, Shinya Sasagawa, Katsuaki Tochibayashi
  • Publication number: 20160093642
    Abstract: A first conductive film overlapping with an oxide semiconductor film is formed over a gate insulating film, a gate electrode is formed by selectively etching the first conductive film using a resist subjected to electron beam exposure, a first insulating film is formed over the gate insulating film and the gate electrode, removing a part of the first insulating film while the gate electrode is not exposed, an anti-reflective film is formed over the first insulating film, the anti-reflective film, the first insulating film and the gate insulating film are selectively etched using a resist subjected to electron beam exposure, and a source electrode in contact with one end of the oxide semiconductor film and one end of the first insulating film and a drain electrode in contact with the other end of the oxide semiconductor film and the other end of the first insulating film are formed.
    Type: Application
    Filed: December 7, 2015
    Publication date: March 31, 2016
    Inventors: Atsuo ISOBE, Yutaka OKAZAKI, Kazuya HANAOKA, Shinya SASAGAWA, Motomu KURATA
  • Patent number: 9299852
    Abstract: A miniaturized semiconductor device in which an increase in power consumption is suppressed and a method for manufacturing the semiconductor device are provided. A highly reliable semiconductor device having stable electric characteristics and a method for manufacturing the semiconductor device are provided. An oxide semiconductor film is irradiated with ions accelerated by an electric field in order to reduce the average surface roughness of a surface of the oxide semiconductor film. Consequently, an increase in the leakage current and power consumption of a transistor can be suppressed. Moreover, by performing heat treatment so that the oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to the surface of the oxide semiconductor film, a change in electric characteristics of the oxide semiconductor film due to irradiation with visible light or ultraviolet light can be suppressed.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: March 29, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kyoko Yoshioka, Junichi Koezuka, Shinji Ohno, Yuichi Sato, Shinya Sasagawa
  • Patent number: 9299815
    Abstract: An object is to provide a semiconductor device in which defects are reduced and miniaturization is achieved while favorable characteristics are maintained. A semiconductor layer is formed; a first conductive layer is formed over the semiconductor layer; the first conductive layer is etched with use of a first resist mask to form a second conductive layer having a recessed portion; the first resist mask is reduced in size to form a second resist mask; the second conductive layer is etched with use of the second resist mask to form source and drain electrodes each having a projecting portion with a tapered shape at the peripheries; a gate insulating layer is formed over the source and drain electrodes to be in contact with part of the semiconductor layer; and a gate electrode is formed in a portion over the gate insulating layer and overlapping with the semiconductor layer.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: March 29, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Motomu Kurata
  • Publication number: 20160087105
    Abstract: A method for manufacturing a semiconductor device, including the steps of forming a semiconductor over a substrate; forming a first conductor over the semiconductor; forming a first insulator over the first conductor; forming a resist over the first insulator; performing light exposure and development on the resist to make a second region and a third region remain and expose part of the first insulator; applying a bias in a direction perpendicular to a top surface of the substrate and generating plasma using a gas containing carbon and halogen; and depositing and etching an organic substance with the plasma. The etching rate of the organic substance is higher than the deposition rate of the organic substance in an exposed part of the first insulator, and the deposition rate of the organic substance is higher than the etching rate of the organic substance in a side surface of the second region.
    Type: Application
    Filed: September 14, 2015
    Publication date: March 24, 2016
    Inventors: Shinya SASAGAWA, Akihisa SHIMOMURA, Katsuaki TOCHIBAYASHI, Yuta ENDO, Shunpei YAMAZAKI
  • Patent number: 9287117
    Abstract: To provide a highly reliable semiconductor device including an oxide semiconductor by suppression of change in its electrical characteristics. Oxygen is supplied from a base insulating layer provided below an oxide semiconductor layer and a gate insulating layer provided over the oxide semiconductor layer to a region where a channel is formed, whereby oxygen vacancies which might be generated in the channel are filled. Further, extraction of oxygen from the oxide semiconductor layer by a source electrode layer or a drain electrode layer in the vicinity of the channel formed in the oxide semiconductor layer is suppressed, whereby oxygen vacancies which might be generated in a channel are suppressed.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: March 15, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Shinya Sasagawa, Tetsuhiro Tanaka
  • Patent number: 9287410
    Abstract: A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a source electrode layer and a drain electrode layer electrically connected to the semiconductor layer, a gate insulating film over the semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer overlapping with part of the semiconductor layer, part of the source electrode layer, and part of the drain electrode layer with the gate insulating film therebetween. A cross section of the semiconductor layer in the channel width direction is substantially triangular or substantially trapezoidal. The effective channel width is shorter than that for a rectangular cross section.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: March 15, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Motomu Kurata, Kazuya Hanaoka, Yoshiyuki Kobayashi, Daisuke Matsubayashi