Patents by Inventor Shinya Sasagawa

Shinya Sasagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150093855
    Abstract: To provide a miniaturized semiconductor device with stable electric characteristics in which a short-channel effect is suppressed. Further, to provide a manufacturing method of the semiconductor device. The semiconductor device (transistor) including a trench formed in an oxide insulating layer, an oxide semiconductor film formed along the trench, a source electrode and a drain electrode which are in contact with the oxide semiconductor film, a gate insulating layer over the oxide semiconductor film, a gate electrode over the gate insulating layer is provided. The lower corner portions of the trench are curved, and the side portions of the trench have side surfaces substantially perpendicular to the top surface of the oxide insulating layer. Further, the width between the upper ends of the trench is greater than or equal to 1 time and less than or equal to 1.5 times the width between the side surfaces of the trench.
    Type: Application
    Filed: December 11, 2014
    Publication date: April 2, 2015
    Inventors: Akihiro ISHIZUKA, Shinya SASAGAWA
  • Publication number: 20150084049
    Abstract: An object is to provide a method for manufacturing a semiconductor device including an oxide semiconductor and having improved electric characteristics. The semiconductor device includes an oxide semiconductor film, a gate electrode overlapping the oxide semiconductor film, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. The method includes the steps of forming a first insulating film including gallium oxide over and in contact with the oxide semiconductor film; forming a second insulating film over and in contact with the first insulating film; forming a resist mask over the second insulating film; forming a contact hole by performing dry etching on the first insulating film and the second insulating film; removing the resist mask by ashing using oxygen plasma; and forming a wiring electrically connected to at least one of the gate electrode, the source electrode, and the drain electrode through the contact hole.
    Type: Application
    Filed: December 3, 2014
    Publication date: March 26, 2015
    Inventors: Akihiro ISHIZUKA, Yutaka YONEMITSU, Shinya SASAGAWA
  • Patent number: 8987727
    Abstract: An object is to provide a semiconductor device in which defects are reduced and miniaturization is achieved while favorable characteristics are maintained. A semiconductor layer is formed; a first conductive layer is formed over the semiconductor layer; the first conductive layer is etched with use of a first resist mask to form a second conductive layer having a recessed portion; the first resist mask is reduced in size to form a second resist mask; the second conductive layer is etched with use of the second resist mask to form source and drain electrodes each having a projecting portion with a tapered shape at the peripheries; a gate insulating layer is formed over the source and drain electrodes to be in contact with part of the semiconductor layer; and a gate electrode is formed in a portion over the gate insulating layer and overlapping with the semiconductor layer.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: March 24, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Motomu Kurata
  • Publication number: 20150079730
    Abstract: An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.
    Type: Application
    Filed: November 20, 2014
    Publication date: March 19, 2015
    Inventors: Hideomi SUZAWA, Shinya SASAGAWA, Taiga MURAOKA
  • Patent number: 8980685
    Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by wet etching in which an etchant is used, and a second etching step is performed by dry etching in which an etching gas is used.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: March 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Shinya Sasagawa, Taiga Muraoka, Shunichi Ito, Miyuki Hosoba
  • Publication number: 20150060848
    Abstract: To provide a highly reliable semiconductor device using an oxide semiconductor. The semiconductor device includes a first electrode layer; a second electrode layer positioned over the first electrode layer and including a stacked-layer structure of a first conductive layer and a second conductive layer; and an oxide semiconductor film and an insulating film positioned between the first electrode layer and the second electrode layer in a thickness direction. The first conductive layer and the insulating film have a first opening portion in a region overlapping with the first electrode layer. The oxide semiconductor film has a second opening portion in a region overlapping with the first opening portion. The second conductive layer is in contact with the first electrode layer exposed in the first opening portion and the second opening portion.
    Type: Application
    Filed: September 4, 2014
    Publication date: March 5, 2015
    Inventors: Shinya SASAGAWA, Motomu KURATA, Katsuaki TOCHIBAYASHI
  • Patent number: 8969144
    Abstract: Described is a method for manufacturing a semiconductor device. A mask is formed over an insulating film and the mask is reduced in size. An insulating film having a projection is formed using the mask reduced in size, and a transistor whose channel length is reduced is formed using the insulating film having a projection. Further, in manufacturing the transistor, a planarization process is performed on a surface of a gate insulating film which overlaps with a top surface of a fine projection. Thus, the transistor can operate at high speed and the reliability can be improved. In addition, the insulating film is processed into a shape having a projection, whereby a source electrode and a drain electrode can be formed in a self-aligned manner.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: March 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Shinya Sasagawa, Akihiro Ishizuka
  • Publication number: 20150056750
    Abstract: A first insulating film in contact with an oxide semiconductor film and a second insulating film are stacked in this order over an electrode film of a transistor including the oxide semiconductor film, an etching mask is formed over the second insulating film, an opening portion exposing the electrode film is formed by etching a portion of the first insulating film and a portion of the second insulating film, the opening portion exposing the electrode film is exposed to argon plasma, the etching mask is removed, and a conductive film is formed in the opening portion exposing the electrode film. The first insulating film is an insulating film whose oxygen is partly released by heating. The second insulating film is less easily etched than the first insulating film and has a lower gas-permeability than the first insulating film.
    Type: Application
    Filed: October 29, 2014
    Publication date: February 26, 2015
    Inventors: Shinya SASAGAWA, Hiroshi FUJIKI, Yoshinori IEDA
  • Patent number: 8956929
    Abstract: In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor layer and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive layer and an interlayer insulating layer are stacked to cover the oxide semiconductor layer, the sidewall insulating layers, and the gate electrode layer. Then, parts of the interlayer insulating layer and the conductive layer over the gate electrode layer are removed by a chemical mechanical polishing method, so that a source electrode layer and a drain electrode layer are formed. Before formation of the gate insulating layer, cleaning treatment is performed on the oxide semiconductor layer.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: February 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuji Egi, Hideomi Suzawa, Shinya Sasagawa
  • Publication number: 20150041805
    Abstract: Provided is a miniaturized transistor having high electrical characteristics. The transistor includes a source electrode layer in contact with one side surface of the oxide semiconductor layer in the channel-length direction and a drain electrode layer in contact with the other side surface thereof. The transistor further includes a gate electrode layer in a region overlapping with a channel formation region with a gate insulating layer provided therebetween and a conductive layer having a function as part of the gate electrode layer in a region overlapping with the source electrode layer or the drain electrode layer with the gate insulating layer provided therebetween and in contact with a side surface of the gate electrode layer. With such a structure, an Lov region is formed with a scaled-down channel length maintained.
    Type: Application
    Filed: September 23, 2014
    Publication date: February 12, 2015
    Inventors: Shinya SASAGAWA, Motomu KURATA
  • Publication number: 20150037932
    Abstract: A semiconductor device which includes an oxide semiconductor and has favorable electrical characteristics is provided. In the semiconductor device, an oxide semiconductor film and an insulating film are formed over a substrate. Side surfaces of the oxide semiconductor film are in contact with the insulating film. The oxide semiconductor film includes a channel formation region and regions containing a dopant between which the channel formation region is sandwiched. A gate insulating film is formed on and in contact with the oxide semiconductor film. A gate electrode with sidewall insulating films is formed over the gate insulating film. A source electrode and a drain electrode are formed in contact with the oxide semiconductor film and the insulating film.
    Type: Application
    Filed: August 14, 2014
    Publication date: February 5, 2015
    Inventors: Shunpei YAMAZAKI, Atsuo ISOBE, Toshihiko SAITO, Takehisa HATANO, Hideomi SUZAWA, Shinya SASAGAWA, Junichi KOEZUKA, Yuichi SATO, Shinji OHNO
  • Patent number: 8946812
    Abstract: To provide a miniaturized semiconductor device with stable electric characteristics in which a short-channel effect is suppressed. Further, to provide a manufacturing method of the semiconductor device. The semiconductor device (transistor) including a trench formed in an oxide insulating layer, an oxide semiconductor film formed along the trench, a source electrode and a drain electrode which are in contact with the oxide semiconductor film, a gate insulating layer over the oxide semiconductor film, a gate electrode over the gate insulating layer is provided. The lower corner portions of the trench are curved, and the side portions of the trench have side surfaces substantially perpendicular to the top surface of the oxide insulating layer. Further, the width between the upper ends of the trench is greater than or equal to 1 time and less than or equal to 1.5 times the width between the side surfaces of the trench.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: February 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihiro Ishizuka, Shinya Sasagawa
  • Publication number: 20150028330
    Abstract: Provided is a semiconductor device in which a deterioration in electrical characteristics which becomes more noticeable as miniaturization can be suppressed. The semiconductor device includes a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a source electrode and a drain electrode in contact with each side surface of the first oxide semiconductor film and the second oxide semiconductor film; a first insulating film and a second insulating film over the source electrode and the drain electrode; a third oxide semiconductor film over the second oxide semiconductor film, the source electrode, and the drain electrode; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with an upper surface of the gate insulating film and facing an upper surface and the side surface of the second oxide semiconductor film.
    Type: Application
    Filed: July 22, 2014
    Publication date: January 29, 2015
    Inventors: Shunpei Yamazaki, Shinya Sasagawa, Suguru Hondo, Hideomi Suzawa
  • Publication number: 20150017541
    Abstract: A power storage device which has high charge/discharge capacity and less deterioration in battery characteristics due to charge/discharge and can perform charge/discharge at high speed is provided. A power storage device includes a negative electrode. The negative electrode includes a current collector and an active material layer provided over the current collector. The active material layer includes a plurality of protrusions protruding from the current collector and a graphene provided over the plurality of protrusions. Axes of the plurality of protrusions are oriented in the same direction. A common portion may be provided between the current collector and the plurality of protrusions.
    Type: Application
    Filed: August 29, 2014
    Publication date: January 15, 2015
    Inventors: Ryota TAJIMA, Shunpei YAMAZAKI, Teppei OGUNI, Takeshi OSADA, Shinya SASAGAWA, Kazutaka KURIKI
  • Publication number: 20150014679
    Abstract: To give favorable electrical characteristics to a semiconductor device. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a pair of electrodes over the semiconductor layer and each electrically connected to the semiconductor layer, a gate electrode over the semiconductor layer, and a gate insulating layer between the semiconductor layer and the gate electrode. The insulating layer includes an island-shaped projecting portion. A top surface of the projecting portion of the insulating layer is in contact with a bottom surface of the semiconductor layer, and is positioned on an inner side of the semiconductor layer when seen from above. The pair of electrodes covers part of a top surface and part of side surfaces of the semiconductor layer. Furthermore, the gate electrode and the gate insulating layer cover side surfaces of the projecting portion of the insulating layer.
    Type: Application
    Filed: July 1, 2014
    Publication date: January 15, 2015
    Inventors: Shinya Sasagawa, Motomu Kurata
  • Patent number: 8932913
    Abstract: To provide a semiconductor device which prevents defects and achieves miniaturization. A projecting portion or a trench (a groove portion) is formed in an insulating layer and a channel formation region of a semiconductor layer is provided in contact with the projecting portion or the trench, so that the channel formation region is extended in a direction perpendicular to a substrate. Thus, miniaturization of the transistor can be achieved and an effective channel length can be extended. In addition, before formation of the semiconductor layer, an upper-end corner portion of the projecting portion or the trench with which the semiconductor layer is in contact is subjected to round chamfering, so that a thin semiconductor layer can be formed with good coverage.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: January 13, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Akihiro Ishizuka
  • Patent number: 8916868
    Abstract: A semiconductor device having a transistor including an oxide semiconductor film is disclosed. In the semiconductor device, the oxide semiconductor film is provided along a trench formed in an insulating layer. The trench includes a lower end corner portion and an upper end corner portion having a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, and the oxide semiconductor film is provided in contact with a bottom surface, the lower end corner portion, the upper end corner portion, and an inner wall surface of the trench. The oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface at least over the upper end corner portion.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: December 23, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Toshinari Sasaki, Shinya Sasagawa, Akihiro Ishizuka
  • Patent number: 8912040
    Abstract: An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: December 16, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Shinya Sasagawa, Taiga Muraoka
  • Publication number: 20140361291
    Abstract: A semiconductor device using oxide semiconductor with favorable electrical characteristics, or a highly reliable semiconductor device is provided. A semiconductor device is manufactured by: forming an oxide semiconductor layer over an insulating surface; forming source and drain electrodes over the oxide semiconductor layer; forming an insulating film and a conductive film in this order over the oxide semiconductor layer and the source and drain electrodes; etching part of the conductive film and insulating film to form a gate electrode and a gate insulating layer, and etching part of the upper portions of the source and drain electrodes to form a first covering layer containing a constituent element of the source and drain electrodes and in contact with the side surface of the gate insulating layer; oxidizing the first covering layer to form a second covering layer; and forming a protective insulating layer containing an oxide over the second covering layer.
    Type: Application
    Filed: June 2, 2014
    Publication date: December 11, 2014
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shinya Sasagawa, Motomu Kurata, Kazuya Hanaoka, Suguru Hondo
  • Patent number: 8906737
    Abstract: An object is to provide a method for manufacturing a semiconductor device including an oxide semiconductor and having improved electric characteristics. The semiconductor device includes an oxide semiconductor film, a gate electrode overlapping the oxide semiconductor film, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. The method includes the steps of forming a first insulating film including gallium oxide over and in contact with the oxide semiconductor film; forming a second insulating film over and in contact with the first insulating film; forming a resist mask over the second insulating film; forming a contact hole by performing dry etching on the first insulating film and the second insulating film; removing the resist mask by ashing using oxygen plasma; and forming a wiring electrically connected to at least one of the gate electrode, the source electrode, and the drain electrode through the contact hole.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: December 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihiro Ishizuka, Yutaka Yonemitsu, Shinya Sasagawa