Abstract: A piezoelectric element includes a substrate; and a first electrode, a first piezoelectric film, a second electrode, a second piezoelectric film, and a third electrode which are provided on the substrate in this order, in which both the first piezoelectric film and the second piezoelectric film contain a perovskite-type oxide containing Pb at an A site and containing Zr, Ti, and M at a B site as a main component, an M composition ratio in the first piezoelectric film is different from an M composition ratio in the second piezoelectric film, and polarization-electric field hysteresis measured for the first piezoelectric film with the first electrode grounded and the second electrode as a drive electrode, and polarization-electric field hysteresis measured for the second piezoelectric film with the second electrode grounded and the third electrode as a drive electrode are shifted in the same electric field direction with respect to origins thereof.

Abstract: A piezoelectric element includes a substrate; and a first electrode, a first piezoelectric film, a second electrode, a second piezoelectric film, and a third electrode which are provided on the substrate in this order, in which both the first piezoelectric film and the second piezoelectric film contain PZT having a metal element M doped thereto, as a main component, one piezoelectric film of the first piezoelectric film and the second piezoelectric film has a spontaneous polarization aligned in a film thickness direction, and in a case where in a hysteresis curve showing polarization-voltage characteristics of the one piezoelectric film, a coercive voltage Vcf+ on a positive side and a coercive voltage Vcf? on a negative side, and in polarization-voltage characteristics of the other piezoelectric film, a coercive voltage Vcr+ on a positive side and a coercive voltage Vcr? on a negative sid, |Vcr++Vcr?|<|Vcf++Vcf?|?0.2 is satisfied.

Abstract: A piezoelectric element includes a substrate, a first electrode, a first piezoelectric film, a second electrode, a second piezoelectric film, and a third electrode, in which both the first piezoelectric film and the second piezoelectric film have spontaneous polarizations aligned in a film thickness direction and directions of the spontaneous polarizations are the same, and in a case where in a hysteresis curve of one piezoelectric film, a coercive voltage Vcf+, a coercive voltage Vcf?, |Vcf+?Vcf?|=?Vcf, and the larger of an absolute value of Vcf+ and an absolute value of Vcf? is denoted by Vcf, and in a hysteresis curve of the other piezoelectric film, a coercive voltage Vcr+, a coercive voltage Vcr?, |Vcr+?Vcr?|=?Vcr, and the larger of an absolute value of Vcr+ and an absolute value Vcr? is denoted by Vcr, ?Vcr<?Vcf?0.2 and Vcr<Vcf?0.2 are satisfied.

Abstract: A piezoelectric element includes a substrate; and a first electrode, a first piezoelectric film, a second electrode, a second piezoelectric film, and a third electrode which are provided on the substrate in this order, in which both the first piezoelectric film and the second piezoelectric film contain a perovskite-type oxide containing Pb Zr, Ti, and M, as a main component, Pb composition ratios in the perovskite-type oxides contained in the first piezoelectric film and the second piezoelectric film are different from each other, and polarization-electric field hysteresis measured for the first piezoelectric film with the first electrode grounded and the second electrode as a drive electrode, and polarization-electric field hysteresis measured for the second piezoelectric film with the second electrode grounded and the third electrode as a drive electrode are shifted in the same electric field direction with respect to origins thereof.

Abstract: An inductor component and a method for manufacturing an inductor component that enables miniaturization of the inductor component. An inductor component includes an annular core; and a coil including a plurality of pin members and wound on the core with neighboring pin members connected to each other. A first pin member and a second pin member both adjacent to each other have a welded part in which an end face of an end part of the first pin member and a peripheral surface of an end part of the second pin member are welded to each other. The welded part is not provided on an outer side edge of the second pin member as viewed from a direction orthogonal to a first plane containing a center line of the end part of the first pin member and a center line of the end part of the second pin member.

Abstract: A semiconductor device with an antenna includes a heat sink having first and second surfaces, a semiconductor chip provided on the second surface and having a circuit surface, a wiring board having a laminate of alternately disposed insulating layers and interconnect layers, and covering side surfaces of the heat sink and the semiconductor chip and the circuit surface, and exposing the first surface, and an antenna provided on the wiring board. The wiring board includes a board connecting part provided on an opposite side from the antenna, a first interconnect electrically connecting the board connecting part and a first terminal provided on the circuit surface, and a second interconnect electrically connecting the antenna and a second terminal provided on the circuit surface.

Abstract: The semiconductor device includes a first semiconductor IC, a second semiconductor IC with a smaller heat generation quantity than the first semiconductor IC, a first heat conduction member covering at least a portion of the first semiconductor IC, a second heat conduction member covering the second semiconductor IC and the first heat conduction member, and a heat dissipation member. The heat dissipation member covers the second heat conduction member and dissipates heat produced from the first semiconductor IC and second semiconductor IC to the exterior. A thermal conductivity of the first heat conduction member is lower than a thermal conductivity of the second heat conduction member in a horizontal direction, which is a direction in which the first semiconductor IC and the second semiconductor IC are arrayed.

Abstract: According to the present disclosure, there is provided a technique capable of preventing a substrate from being warped or cracked due to a heat treatment process. According to one aspect thereof, there is provided a substrate processing apparatus including: a process chamber in which a plurality of substrates accommodated in a substrate retainer are processed; an electromagnetic wave generator configured to supply an electromagnetic wave into the process chamber; and a gas supplier configured to supply a cooling gas is supplied to between adjacent substrates among the plurality of substrates via a plurality of gas supply ports provided so as to correspond to an interval of the plurality of substrates accommodated in the substrate retainer.

Abstract: A semiconductor apparatus includes a substrate, a plurality of heat generating elements mounted on the substrate, a heat dissipation member fixed to the substrate and disposed such that the heat generating elements are interposed between the heat dissipation member and the substrate, at least one first heat conduction member provided on a first surface of the heat dissipation member, the first surface facing the heat generating elements, and a plurality of second heat conduction members each provided on a second surface of a corresponding one of the heat generating elements, the second surface facing the heat dissipation member, wherein the at least one first heat conduction member and the second heat conduction members are in contact with each other at an interface between opposing surfaces thereof.

Abstract: There is provided a technique that includes: loading a substrate in which a treatment target film and an action target film are formed into a process chamber; irradiating the action target film with an electromagnetic wave; and causing the action target film to generate heat by the irradiation with the electromagnetic wave and modifying the treatment target film with a directionality by heating the treatment target film with the heat generated by the action target film.

Abstract: There is provided a technique, which includes: a process chamber where a substrate is processed; a microwave oscillator configured to supply microwaves to the process chamber; and a controller configured to be capable of controlling the microwave oscillator to perform: a heating process where the substrate is heated with a first microwave, among the supplied microwaves, supplied at a first microwave power so that a process of supplying the first microwave during a supply time and a process of stopping the supply of the first microwave during a stop time shorter than the supply time are performed a predetermined number of times or for a first predetermined time; and a modifying process in which the substrate is supplied with a second microwave, among the supplied microwaves, at a second microwave power higher than the first microwave power for a second predetermined time while maintaining the second microwave power.

Abstract: In a carrier core material according to the present invention, the volume moment mean D [4, 3] of O. Bluntness measured with an injection type image analysis particle size distribution meter is equal to or greater than 65% and equal to or less than 80%, and the volume moment mean D [4, 3] of ISO Roundness is equal to or greater than 80% and equal to or less than 86%. In this way, it is possible to suppress development memory and carrier adherence.

Abstract: There is provided a technique that include: a process chamber configured to process a substrate at which at least one target film and a heat assist film are formed; and an electromagnetic wave generator configured to supply an electromagnetic wave into the process chamber, wherein when the substrate is irradiated with the electromagnetic wave, the heat assist film generates heat and the at least one target film is modified by the heat.

Abstract: The semiconductor device includes a first semiconductor IC, a second semiconductor IC with a smaller heat generation quantity than the first semiconductor IC, a first heat conduction member covering at least a portion of the first semiconductor IC, a second heat conduction member covering the second semiconductor IC and the first heat conduction member, and a heat dissipation member. The heat dissipation member covers the second heat conduction member and dissipates heat produced from the first semiconductor IC and second semiconductor IC to the exterior. A thermal conductivity of the first heat conduction member is lower than a thermal conductivity of the second heat conduction member in a horizontal direction, which is a direction in which the first semiconductor IC and the second semiconductor IC are arrayed.

Abstract: Described herein is a technique capable of uniformly processing a substrate. According to one aspect of the technique, there is provided a substrate processing apparatus including: a process chamber in which a substrate is processed; a microwave generator configured to supply a microwave to the process chamber to perform a heat treatment on the substrate; a substrate retainer configured to accommodate the substrate and a heat retainer provided above the substrate and retaining a temperature of the substrate heated by the microwave; and a first ring plate provided on an outer circumference of the heat retainer and whose outer diameter is greater than that of the substrate.

Abstract: There is provided a technique includes: a process chamber in which a substrate is processed; a plurality of microwave supply sources configured to supply predetermined microwaves for heating the substrate in the process chamber; and a controller configured to control the microwave supply sources such that while keeping constant a sum of outputs of the microwaves respectively supplied to the substrate from the plurality of microwave supply sources, at least one of the plurality of microwave supply sources is turned off, and periods in which the at least one of the plurality of microwave supply sources is turned off are different from each other.

Abstract: An aspect of the present invention is a color filter for converting an incident light from one surface of the color filter to a light having a wavelength different from that of the incident light and permitting the converted light to exit from another surface of the color filter, the color filter comprising: a bank having a plurality of opening portions and being formed to extend from the another surface to the one surface of the color filter; a plurality of pixel portions formed in the respective opening portions; and a reflective film formed so as to cover at least part of the side of the bank.

Abstract: A clearance narrowing material containing a brush-shaped polymer chain aggregate formed of multiple polymer chains immobilized on a substrate. The invention provides a clearance narrowing material which can effectively prevent fluid leakage through a clearance and which does not disturb relative movement of members to form a clearance, and can realize an article in which fluid leakage through a clearance can be effectively prevented and the members to form a clearance can move smoothly.

Abstract: A semiconductor relay module includes first to third semiconductor relays, first to third input terminals, first to third output terminals, a first connection line, and a first monitor terminal connected to the first connection line. A first input circuit of the first semiconductor relay and a second input circuit of the second semiconductor relay are connected to the first and second input terminals. A third input circuit of the third semiconductor relay is connected to the first or second input terminal and the third input terminal. A first output circuit of the first semiconductor relay is connected to the first output terminal and the first connection line. A second output circuit of the second semiconductor relay is connected to the second output terminal and the first connection line. A third output circuit of the third semiconductor relay is connected to the third output terminal and the first connection line.

Abstract: A semiconductor relay module includes first to third semiconductor relays, first to third input terminals, first to third output terminals, and a first connection line. A first input circuit of the first semiconductor relay and a second input circuit of the second semiconductor relay are connected to the first and second input terminals. The first and second input circuits are connected in series. A third input circuit of the third semiconductor relay is connected to the first or second input terminal and the third input terminal. A first output circuit of the first semiconductor relay is connected to the first output terminal and the first connection line. A second output circuit of the second semiconductor relay is connected to the second output terminal and the first connection line. A third output circuit of the third semiconductor relay is connected to the third output terminal and the first connection line.