Patents by Inventor Shiro Dosho
Shiro Dosho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8665129Abstract: An oversampling A/D converter with a few operational amplifiers is configured using a complex second-order integrator including first and second second-order integrators and first and second coupling circuits configured to couple these integrators together. Each of the second-order integrators includes an operational amplifier, four resistance elements, and three capacitance elements. The first coupling circuit cross-couples one of two serially-connected capacitance elements inserted between the inverted input terminal and output terminal of the operational amplifier in the first second-order integrator to the counterpart in the second second-order integrator using two resistance elements. The second coupling circuit cross-couples the other capacitance element in the first second-order integrator to the counterpart in the second second-order integrator using two resistance elements.Type: GrantFiled: March 2, 2012Date of Patent: March 4, 2014Assignee: Panasonic CorporationInventor: Shiro Dosho
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Publication number: 20140055294Abstract: Two resistive elements and a capacitive element are coupled between a first node and each of an inverting input terminal of an operational amplifier, an output terminal of the operational amplifier, and a common node. A resistive element and a capacitive element are coupled between the first node and a signal input terminal. Two capacitive elements and a resistive element are coupled between a second node and each of the inverting input terminal, the output terminal, and the common node. Two capacitive elements are coupled between the second node and each of the signal input terminal, and the common node.Type: ApplicationFiled: November 5, 2013Publication date: February 27, 2014Applicant: PANASONIC CORPORATIONInventors: Shiro DOSHO, Kazuo MATSUKAWA, Yosuke MITANI
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Publication number: 20130335251Abstract: A time-to-digital conversion circuit for converting a time difference between two input signals to a 1-bit digital value, and adjusting the time difference between the two input signals to generate two output signals includes: a phase comparator configured to compare phases of the two input signals with each other to generate the digital value; a phase selector configured to output one of the two input signals which has a leading phase as a first signal, and the other of the two input signals which has a lagging phase as a second signal; and a delay unit configured to output the first signal with a delay, wherein the time-to-digital conversion circuit outputs the signal output from the delay unit and the second signal as the two output signals.Type: ApplicationFiled: July 15, 2013Publication date: December 19, 2013Applicant: Panasonic CorporationInventors: Shiro DOSHO, Masao TAKAYAMA, Takuji MIKI
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Patent number: 8604956Abstract: Two resistive elements and a capacitive element are coupled between a first node and each of an inverting input terminal of an operational amplifier, an output terminal of the operational amplifier, and a common node. A resistive element and a capacitive element are coupled between the first node and a signal input terminal. Two capacitive elements and a resistive element are coupled between a second node and each of the inverting input terminal, the output terminal, and the common node. Two capacitive elements are coupled between the second node and each of the signal input terminal, and the common node.Type: GrantFiled: March 28, 2011Date of Patent: December 10, 2013Assignee: Panasonic CorporationInventors: Shiro Dosho, Kazuo Matsukawa, Yosuke Mitani
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Publication number: 20130249718Abstract: An oversampling A/D converter includes a first filter including a first resistive element, a first capacitive element, a second resistive element, an operational amplifier, and a second capacitive element; a second filter receiving an output of the first filter; a third filter including a third resistive element, a third capacitive element, and a fourth resistive element; a quantizer receiving an output of the third filter and generating a digital signal; and a D/A converter converting the digital signal to an analog current signal. The D/A converter inputs the generated analog current signal to an inverting input terminal of the operational amplifier.Type: ApplicationFiled: May 20, 2013Publication date: September 26, 2013Applicant: PANASONIC CORPORATIONInventors: Shiro Dosho, Kazuo Matsukawa, Masao Takayama, Yosuke Mitani
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Patent number: 8466820Abstract: An oversampling A/D converter includes a first filter including a first resistive element, a first capacitive element, a second resistive element, an operational amplifier, and a second capacitive element; a second filter receiving an output of the first filter; a third filter including a third resistive element, a third capacitive element, and a fourth resistive element; a quantizer receiving an output of the third filter and generating a digital signal; and a D/A converter converting the digital signal to an analog current signal. The D/A converter inputs the generated analog current signal to an inverting input terminal of the operational amplifier.Type: GrantFiled: February 11, 2011Date of Patent: June 18, 2013Assignee: Panasonic CorporationInventors: Shiro Dosho, Kazuo Matsukawa, Masao Takayama, Yosuke Mitani
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Publication number: 20120313803Abstract: In a time-to-digital conversion stage, a time-to-digital conversion circuit outputs an n-bit digital signal, which represents an integer value ranging from ?(2n-1?1) to +(2n-1?1), based on a phase difference between a first and a second signals input thereto; a time difference amplifier circuit amplifies the phase difference between the first and the second signals 2n-1 times, and outputs two signals having an amplified phase difference therebetween; a delay adjustment circuit adds a phase difference dependent on the digital signal to the two signals output from the time difference amplifier circuit, and outputs another two signals; an output detection circuit detects that the delay adjustment circuit has output the another two signals, and outputs a detection signal; and a storage circuit latches the digital signal in synchronism with the detection signal. Multi-stage coupling of the time-to-digital conversion stages forms a pipeline time-to-digital converter.Type: ApplicationFiled: August 20, 2012Publication date: December 13, 2012Applicant: Panasonic CorporationInventors: Shiro DOSHO, Takuji Miki
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Publication number: 20120262320Abstract: Two T filters, one of which includes two resistive elements and one capacitive element and the other of which includes two capacitive elements and one resistive element, are inserted in a negative-feedback section of an operational amplifier, and a resistive element and a capacitive element are connected between each of intermediate nodes and a signal input terminal. A resistive element and a capacitive element which are connected to each other in parallel are connected between the signal input terminal and an inverting input terminal of the operational amplifier. With this configuration, overall admittances where elements connected to the corresponding intermediate nodes are in parallel connection are equal to each other.Type: ApplicationFiled: June 27, 2012Publication date: October 18, 2012Applicant: Panasonic CorporationInventors: Yosuke Mitani, Kazuo Matsukawa, Masao Takayama, Koji Obata, Shiro Dosho
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Patent number: 8258990Abstract: An integrator includes an operational amplifier, a first filter connected to an inverting input terminal of the operational amplifier, and a second filter connected between the inverting input terminal and an output terminal of the operational amplifier. The first filter includes n resistive elements connected in series, and (n?1) capacitive elements each having one end connected to an interconnecting node of the resistive elements and the other end connected to ground. The second filter includes n capacitive elements connected in series, and (n?1) resistive elements each having one end connected to an interconnecting node of the capacitive elements and the other end connected to ground.Type: GrantFiled: September 22, 2010Date of Patent: September 4, 2012Assignee: Panasonic CorporationInventors: Shiro Dosho, Takashi Morie, Kazuo Matsukawa, Yosuke Mitani, Masao Takayama
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Patent number: 8212624Abstract: An oscillator circuit increases and reduces signal levels of first and second oscillation signals in a complementary manner in response to a transition of a signal level of a reference clock. An oscillation control circuit compares each of the signal levels of the first and second oscillation signals to a comparison voltage, and causes the signal level of the reference clock to transition according to results of the comparison. A reference control circuit increases or reduces the comparison voltage so that a difference between a signal level of an intermediate signal which is proportional to respective swings of the first and second oscillation signals and a reference voltage is reduced.Type: GrantFiled: February 7, 2011Date of Patent: July 3, 2012Assignee: Panasonic CorporationInventors: Yusuke Tokunaga, Shiro Sakiyama, Akinori Matsumoto, Shiro Dosho
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Publication number: 20120161990Abstract: A high order integrator is configured using an operational amplifier, a first filter connected between an input terminal of the integrator and an inverted input terminal of the operational amplifier, and a second filter connected between the inverted input terminal and output terminal of the operational amplifier. The first filter includes n serially-connected first resistance elements, n-1 first capacitance elements each connected between each interconnecting node of the first resistance elements and the ground, and n-1 second resistance elements each connected between each interconnecting node of the first resistance elements and the ground. The second filter includes n serially-connected second capacitance elements, n-1 third resistance elements each connected between each interconnecting node of the second capacitance elements and the ground, and n-1 third capacitance elements each connected between each interconnecting node of the second capacitance elements and the ground.Type: ApplicationFiled: March 2, 2012Publication date: June 28, 2012Applicant: Panasonic CorporationInventor: Shiro Dosho
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Publication number: 20120161999Abstract: An oversampling A/D converter with a few operational amplifiers is configured using a complex second-order integrator including first and second second-order integrators and first and second coupling circuits configured to couple these integrators together. Each of the second-order integrators includes an operational amplifier, four resistance elements, and three capacitance elements. The first coupling circuit cross-couples one of two serially-connected capacitance elements inserted between the inverted input terminal and output terminal of the operational amplifier in the first second-order integrator to the counterpart in the second second-order integrator using two resistance elements. The second coupling circuit cross-couples the other capacitance element in the first second-order integrator to the counterpart in the second second-order integrator using two resistance elements.Type: ApplicationFiled: March 2, 2012Publication date: June 28, 2012Applicant: Panasonic CorporationInventor: Shiro DOSHO
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Patent number: 8130608Abstract: In a coupled ring oscillator including q ring oscillators each including p inverter circuits connected together to form a ring shape, and a phase coupling ring including (p×q) phase coupling circuits each of which is configured to couple an output of one of the p inverter circuits of one of the q ring oscillators to an output of one of the p inverter circuits of another one of the q ring oscillators in a predetermined phase relationship, and which are connected together to form a ring shape, for at least one group made up of one of the p inverter circuits in each of the q ring oscillators, outputs of the q inverter circuits belonging to the at least one group are fixed in phase with one another, the q ring oscillators are caused to oscillate in the in-phase fixed state, and then, the outputs of the q inverter circuits are released from the in-phase fixed state.Type: GrantFiled: December 14, 2010Date of Patent: March 6, 2012Assignee: Panasonic CorporationInventors: Akinori Matsumoto, Shiro Sakiyama, Shiro Dosho, Yusuke Tokunaga, Takashi Morie
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Publication number: 20110254718Abstract: An integrator is provided which can reduce a disturbance in the current waveform of a current DA converter in order to improve the SNR of a ?? modulator, for example. The integrator includes an operational amplifier, and feedback paths provided in parallel between the output terminal and inverting input terminal of the operational amplifier. In one of the feedback paths, an integrating capacitor and at least one resistor are connected in series. In the other feedback path, a second integrating capacitor whose capacitance value is smaller than that of the integrating capacitor is provided.Type: ApplicationFiled: June 22, 2011Publication date: October 20, 2011Applicant: PANASONIC CORPORATIONInventors: Kazuo MATSUKAWA, Shiro DOSHO, Yosuke MITANI, Koji OBATA
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Patent number: 8040168Abstract: The charge pump circuit includes: a first switch for controlling either one of push operation and pull operation based on a first control signal; a current mirror circuit composed of a transistor different in attribute from the first switch; and a second switch composed of a transistor same in characteristic as a transistor constituting the first switch, for controlling input of a current into the current mirror circuit based on a second control. The other operation, the push operation or the pull operation, is performed with a current output from the current mirror circuit.Type: GrantFiled: July 26, 2005Date of Patent: October 18, 2011Assignee: Panasonic CorporationInventors: Shiro Sakiyama, Yusuke Tokunaga, Shiro Dosho, Toru Iwata, Takashi Hirata
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Patent number: 8013650Abstract: A phase adjustment circuit includes first to nth two-phase adjustment circuits. Each two-phase adjustment circuit includes a first logic circuit for performing logical sum of two input signals, a second logic circuit for performing logical product of the two input signals, a first delay circuit having a signal delay equal to that of the second logic circuit and configured to delay a signal output from the first logic circuit, and a second delay circuit having a signal delay equal to that of the first logic circuit and configured to delay a signal output from the second logic circuit. Two signals output from two of the two-phase adjustment circuits in a certain stage are input into one of the two-phase adjustment circuits in the next stage.Type: GrantFiled: September 1, 2006Date of Patent: September 6, 2011Assignee: Panasonic CorporationInventors: Shiro Dosho, Shiro Sakiyama, Yusuke Tokunaga, Seiji Watanabe, Hiroshi Koshida
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Publication number: 20110200077Abstract: In a DSM including a loop in which an output signal of a quantizer is digitally processed, and fed back through a DAC to an analog filter, the quantizer quantizes an analog signal from an analog filter section to output a digital signal. The digital signal from the quantizer is digitally processed in a first-order recursive filter circuit including a variable gain amplifier and a delay element. A LUT receives both the digital signal from the quantizer and a table control signal, which is an output signal from the recursive filter circuit, and stores in advance compensation values corresponding to the both signals. A compensation value from the LUT is used to provide a digital output signal compensated for a delay. The digital output signal is converted into an analog signal in the DAC, and then subtracted from an analog input signal in the analog filter section.Type: ApplicationFiled: April 26, 2011Publication date: August 18, 2011Applicant: PANASONIC CORPORATIONInventors: Yosuke MITANI, Kazuo Matsukawa, Masao Takayama, Shiro Dosho
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Publication number: 20110169677Abstract: Two resistive elements and a capacitive element are coupled between a first node and each of an inverting input terminal of an operational amplifier, an output terminal of the operational amplifier, and a common node. A resistive element and a capacitive element are coupled between the first node and a signal input terminal. Two capacitive elements and a resistive element are coupled between a second node and each of the inverting input terminal, the output terminal, and the common node. Two capacitive elements are coupled between the second node and each of the signal input terminal, and the common node.Type: ApplicationFiled: March 28, 2011Publication date: July 14, 2011Applicant: PANASONIC CORPORATIONInventors: Shiro DOSHO, Kazuo Matsukawa, Yosuke Mitani
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Patent number: 7978013Abstract: A constant determination unit (90) determines various constants, that are the magnitude of a charge current outputted from a charge pump circuit (30), the time constant of a loop filter (40), and the gain of a voltage controlled oscillator (50), so as to make the proportionality constant of a natural frequency of a phase locked loop circuit for the input frequency of the phase locked loop circuit and the damping factor to be predetermined values, and outputs various control signals based on the determined constants. The charge pump circuit (30), the loop filter (40), and the voltage controlled oscillator (50) modify the magnitude of the charge current, the time constant, and the gain, respectively, in accordance with control signals outputted from the constant determination unit (90).Type: GrantFiled: October 25, 2006Date of Patent: July 12, 2011Assignee: Panasonic CorporationInventors: Shiro Dosho, Kazuaki Sogawa, Yuji Yamada, Naoshi Yanagisawa
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Publication number: 20110140754Abstract: An oscillator circuit increases and reduces signal levels of first and second oscillation signals in a complementary manner in response to a transition of a signal level of a reference clock. An oscillation control circuit compares each of the signal levels of the first and second oscillation signals to a comparison voltage, and causes the signal level of the reference clock to transition according to results of the comparison. A reference control circuit increases or reduces the comparison voltage so that a difference between a signal level of an intermediate signal which is proportional to respective swings of the first and second oscillation signals and a reference voltage is reduced.Type: ApplicationFiled: February 7, 2011Publication date: June 16, 2011Applicant: PANASONIC CORPORATIONInventors: Yusuke TOKUNAGA, Shiro SAKIYAMA, Akinori MATSUMOTO, Shiro DOSHO