Abstract: A constant determination unit (90) determines various constants, that are the magnitude of a charge current outputted from a charge pump circuit (30), the time constant of a loop filter (40), and the gain of a voltage controlled oscillator (50), so as to make the proportionality constant of a natural frequency of a phase locked loop circuit for the input frequency of the phase locked loop circuit and the damping factor to be predetermined values, and outputs various control signals based on the determined constants. The charge pump circuit (30), the loop filter (40), and the voltage controlled oscillator (50) modify the magnitude of the charge current, the time constant, and the gain, respectively, in accordance with control signals outputted from the constant determination unit (90).

Abstract: A transconductor for receiving a differential voltage signal and outputting a differential current signal, includes two transconductors for receiving the differential voltage signal and outputting a single-end current signal. An inversion input terminal of one of the two transconductors is connected with a non-inversion input terminal of the other. The transconductor outputs a current signal output from each of the two transconductors as the differential current signal.

Abstract: An A/D converter includes: a plurality of A/D conversion circuits (10a, 10b); an input selection section (20) for selecting the A/D conversion circuit that is not executing A/D conversion to supply analog amounts obtained by sample-holding an input signal; and an output selection section (30) for selecting the A/D conversion circuit that is not executing A/D conversion to output digital amounts obtained from the selected one. Each A/D conversion circuit includes: an input memory portion (11) for sequentially storing the supplied analog amounts in a plurality of analog memory elements (111); an A/D conversion portion (12) having a plurality of A/D conversion elements (121) for converting the analog amounts stored in the analog memory elements to digital amounts; and a shift output portion (13), having a plurality of registers (131) receiving the digital amounts from the A/D conversion elements to hold the digital amounts, for shifting and outputting the digital amounts held in the registers.

Abstract: In a device for generating a clock signal having a desired phase from input multi-phase clock signals, an intermediate clock generator generates, by using one of the input multi-phase clock signals as a reference clock signal, multi-phase intermediate clock signals in which one cycle is equal to a plurality of cycles of the reference clock signal. A first phase selector selects one of the multi-phase intermediate clock signals. A second phase selector selects one of the multi-phase clock signals. A latch circuit latches the intermediate clock signal selected by the first phase selector with the clock signal selected by the second phase selector.

Abstract: Each of n level shifters (LS0 to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0 to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0 to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°<X<180°). The phase amounts X of the n level shifters (LS0 to LS7) are equal to each other.

Abstract: A write compensation circuit of a recording device includes a first delay portion driven by a first driving voltage, for receiving a clock signal, delaying the clock signal by a first delay time, and outputting the delayed clock signal, and a voltage supplying portion for supplying the first driving voltage to the first delay portion in such a manner that the first delay time is substantially equal to a clock period of the clock signal.

Abstract: A successive approximation type A-to-D converter includes a cyclic D-to-A converter (11), a comparator (12) for comparing an analog value with an output value of the D-to-A converter (11), and memory means (13) for sequentially storing an output value of the comparator (12) and supplying the stored value to the D-to-A converter (11) in a reverse order.

Abstract: A current driving device includes a reference current source, a first MISFET connected to the reference current source, a plurality of current distribution MISFETs which constitutes a current mirror together with the first MISFET and distributes a reference current, a current input MISFET connected to the current distribution MISFETs, and a plurality of current supply sections each of which includes MISFETs constituting a current mirror circuit together with the current input MISFET and supplies a driving current for a pixel circuit. With the plurality of current distribution MISFETs provided, change in gate the potential of MISFETs in the current supply section can be suppressed, so that the generation of a crosstalk in a display device can be suppressed.

Abstract: In a filter adjustment circuit for an analog filter circuit such as a Gm-C filter, an input signal IS from a reference signal generation circuit 1 is inputted to a Gm-C filter 2 to be filtered and then converted by a conversion circuit 3 to a digital signal. A reference signal RS from the reference signal generation circuit 1 is converted by a conversion circuit 4 to a digital signal. The two converted signals are held in time series in a holding circuit 5. A timing generation circuit 6 generates an update timing signal en based on a reference time-series signal ref from the holding circuit 5. A control signal generation circuit 7 generates a control signal CS based on the reference time-series signal ref and a filter output time-series signal tgt, each from the holding circuit 5. The control signal CS is inputted to the Gm-C filter 2 in response to the update timing signal en to adjust the gain of the Gm-C filter 2.

Abstract: A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.

Abstract: A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.

Abstract: A loop filter (30) includes a first capacitor (31) provided between an input terminal for a current signal and a reference voltage, a switched capacitor circuit (32) provided between the input terminal and the first capacitor (31) and a second capacitor (33) provided in parallel to the first capacitor (31) and the switched capacitor circuit (32). In the switched capacitor circuit (32), when a third capacitor (321) is connected to the first capacitor (31), a fourth capacitor (322) is connected to the second capacitor (33). In the loop filter (30) having the above-described configuration, a capacitance value of the second capacitor (33) is set to be larger than respective capacitance values of the third and fourth capacitors (321 and 322).

Abstract: A charge pumping circuit includes a first switch for controlling one of push and pull operations in accordance with a first control signal; a current mirror circuit constructed from transistors each having a different polarity from the first switch; a second switch for controlling current input to the current mirror circuit in accordance with a second control signal, the second switch being constructed from a transistor having the same characteristic as a transistor used for constructing the first switch; a first MOS capacitor one end of which is connected to an input side of the current mirror circuit; a second MOS capacitor receiving, at one end thereof, a current concerned with the push and pull operations; and a voltage buffer connected to the first and second MOS capacitors. The other of the push and pull operations is performed with an output current of the current mirror circuit.

Abstract: In a filter adjustment circuit for an analog filter circuit such as a Gm-C filter, an input signal IS from a reference signal generation circuit 1 is inputted to a Gm-C filter 2 to be filtered and then converted by a conversion circuit 3 to a digital signal. A reference signal RS from the reference signal generation circuit 1 is converted by a conversion circuit 4 to a digital signal. The two converted signals are held in time series in a holding circuit 5. A timing generation circuit 6 generates an update timing signal en based on a reference time-series signal ref from the holding circuit 5. A control signal generation circuit 7 generates a control signal CS based on the reference time-series signal ref and a filter output time-series signal tgt, each from the holding circuit 5. The control signal CS is inputted to the Gm-C filter 2 in response to the update timing signal en to adjust the gain of the Gm-C filter 2.

Abstract: A time required for an output voltage of a source follower to rise from Low to a predetermined voltage depends on a bias voltage. Therefore, by setting a converged voltage of an output voltage to be high by increasing the bias voltage, the time required to rise up to the predetermined voltage can be reduced. Therefore, a first source follower which is biased so that the converged value of the output voltage becomes a predetermined Hi voltage when an input data signal goes from Low to Hi, and a second source follower which is biased so as to become the Hi voltage after a period of one clock when an input data signal goes from Low to Hi, are used. The two source followers are operated with appropriate timing.

Abstract: A coupled ring oscillator includes n ring oscillators (20) each including m inverter circuits (10), and a phase-coupling loop (40) in which m×n phase-coupling circuits (30), each of which couples signal phases at two points in a certain phase mode, are connected with each other to form a loop. Connection points at which the inverter circuits (10) are connected with each other and the connection points at which the phase-coupling circuits (30) are connected with each other are connected bijectively; and each of the inverter circuits (10) is connected between two points that divide the phase-coupling circuits (30) into two parts at a certain ratio.

Abstract: A switched capacitor filter comprises three switched capacitor circuits. Each switched capacitor circuit has a capacitance. A first state that the capacitance is connected to an input end of a current signal, a second state that the capacitance is connected to an output end of a voltage signal, and a third state that the capacitance is connected to a side of a filter capacitance, are cycled. These three switched capacitor circuits are operated under an interleave control so that the first to third states do not each overlap between the three switched capacitor circuits.

Abstract: The loop filter in the PLL includes: a filter circuit (first partial circuit) including a capacitive element, one end of the first partial circuit being connected to an output terminal of a charge pump circuit, a voltage for controlling a voltage-controlled oscillator being output from the other end of the first partial circuit; a voltage buffer circuit to which a voltage at a predetermined node in the filter circuit is input; and a filter circuit (second partial circuit), one end of the second partial circuit being connected to the output terminal of the charge pump circuit, the other end being connected to an output terminal of the voltage buffer circuit.

Abstract: The phase-locked loop circuit includes a gain setting circuit for setting a gain of a voltage controlled oscillator, and a time-constant setting circuit for setting a time constant, which is determined by the amount of current in a charge pump circuit and a capacitance value of a loop filter. The gain setting circuit sets the gain to a predetermined value, and the time-constant setting circuit sets the time constant to a predetermined value, whereby the loop band width of the phase-locked loop circuit is set to a desired value.

Abstract: A ladder filter includes multiple inductor sections, each including voltage-controlled current sources and capacitors. A second signal input terminal is provided for the filter separately from an ordinary signal input terminal and a signal, which has been input through the second terminal, is supplied to one of the voltage-controlled current sources by way of a gain calculator. By adjusting the gain obtained by the gain calculator to an appropriate value, the ladder filter can make the numerator of its transfer function freely definable.