Patents by Inventor Shirou Ozaki

Shirou Ozaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10508343
    Abstract: An etching method includes: applying a radiation to an etching aqueous solution; and etching a material to be etched by using the etching aqueous solution irradiated with the radiation.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: December 17, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Shirou Ozaki
  • Patent number: 10468514
    Abstract: A semiconductor device includes: a nitride semiconductor multilayer; an insulating film disposed on the nitride semiconductor multilayer; and a gate electrode disposed on the insulating film, wherein the nitride semiconductor multilayer has a first oxidized region near an interface with a region of the insulating film below the gate electrode, the first oxidized region having an oxygen concentration higher than an oxygen concentration of a region near an interface with a region of the insulating film other than below the gate electrode.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: November 5, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Naoya Okamoto
  • Publication number: 20190326404
    Abstract: A semiconductor device includes a substrate, a first semiconductor layer formed over the substrate, the first semiconductor layer being composed of a nitride semiconductor, a second semiconductor layer formed over the first semiconductor layer, the second semiconductor layer being composed of a nitride semiconductor and a gate electrode, a source electrode, and a drain electrode that are formed over the second semiconductor layer, wherein the source electrode including a plurality of protrusions that penetrate into the second semiconductor layer, and the protrusions having a side surface inclined with respect to a surface of the first semiconductor layer.
    Type: Application
    Filed: April 8, 2019
    Publication date: October 24, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Yusuke Kumazaki, Toshihiro Ohki, Kozo Makiyama, Shirou OZAKI, Yuichi Minoura
  • Publication number: 20190244821
    Abstract: A semiconductor device includes: a first semiconductor layer formed, on a substrate, of a nitride semiconductor; a second semiconductor layer formed, on the first semiconductor layer, of a nitride semiconductor; a source electrode formed on the second semiconductor layer; a drain electrode formed on the second semiconductor layer; a metal oxide film formed, between the source electrode and the drain electrode, on the second semiconductor layer; and a gate electrode formed on the metal oxide film. The metal oxide film includes AlOx and InOx. AlOx/InOx in the metal oxide film is greater than or equal to 3.
    Type: Application
    Filed: April 16, 2019
    Publication date: August 8, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Shirou OZAKI, Kozo Makiyama, NAOYA OKAMOTO
  • Patent number: 10312094
    Abstract: A semiconductor device includes: a first semiconductor layer formed, on a substrate, of a nitride semiconductor; a second semiconductor layer formed, on the first semiconductor layer, of a nitride semiconductor; a source electrode formed on the second semiconductor layer; a drain electrode formed on the second semiconductor layer; a metal oxide film formed, between the source electrode and the drain electrode, on the second semiconductor layer; and a gate electrode formed on the metal oxide film. The metal oxide film includes AlOx and InOx. AlOx/InOx in the metal oxide film is greater than or equal to 3.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: June 4, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Kozo Makiyama, Naoya Okamoto
  • Patent number: 10312344
    Abstract: A semiconductor device includes a first semiconductor layer formed of a compound semiconductor, provided over a substrate; a second semiconductor layer formed of a compound semiconductor including In and Al, provided over the first semiconductor layer; source and drain electrodes provided on the second semiconductor layer; and a gate electrode provided between the source and drain electrodes, on the second semiconductor layer. The compound semiconductor in the second semiconductor layer has a first In composition ratio in a region on a side facing the substrate and a second In composition ratio in a region on an opposite side, the second In composition ratio being lower than the first In composition ratio, and the source and drain electrodes are provided in contact with the region having the first In composition ratio, and the gate electrode is provided on the region having the second In composition ratio.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: June 4, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Shirou Ozaki
  • Patent number: 10276703
    Abstract: A compound semiconductor device includes: a carrier transit layer; a carrier supply layer over the carrier transit layer; a source electrode and a drain electrode above the carrier supply layer; a gate electrode above the carrier supply layer between the source electrode and the drain electrode; and a first insulating film and a second insulating film above the carrier supply layer between the gate electrode and the drain electrode. The gate electrode includes a portion above the second insulating film, the second insulating film covers a side surface of the first insulating film from the drain electrode side, and a second concentration of electron traps in the second insulating film is higher than a first concentration of electron traps in the first insulating film.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: April 30, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Youichi Kamada, Shirou Ozaki
  • Patent number: 10276671
    Abstract: A semiconductor device includes a compound semiconductor layer, a gate electrode, and first and second insulating layers. The first insulating layer covers the gate electrode on the compound semiconductor layer and has a cavity that surrounds the gate electrode. The second insulating layer is provided on the first insulating layer and has an opening at a position corresponding to the cavity. A part of the second insulating layer, which is provided on the first insulating layer that covers the gate electrode, corresponding to the cavity is removed via the opening, so that the generation of parasitic capacitance due to the second insulating layer is suppressed.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: April 30, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Shirou Ozaki
  • Patent number: 10192964
    Abstract: A compound semiconductor device includes: a carrier transit layer; a carrier supply layer over the carrier transit layer; a source electrode and a drain electrode above the carrier supply layer; a gate electrode above the carrier supply layer between the source electrode and the drain electrode; and a first insulating film, a second insulating film, and a third insulating film above the carrier supply layer between the gate electrode and the drain electrode. The gate electrode includes a portion above the third insulating film, a first concentration of electron traps in the first insulating film is higher than a second concentration of electron traps in the second insulating film, and a third concentration of electron traps in the third insulating film is higher than the second concentration of the electron traps in the second insulating film.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: January 29, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Youichi Kamada, Shirou Ozaki
  • Publication number: 20180342590
    Abstract: A semiconductor device includes: a semiconductor layer; a first insulating film which covers a surface of the semiconductor layer; a first adhering film which is formed on a surface of the first insulating film and contains a carbonyl group; and a second insulating film which covers a surface of the first adhering film and has a lower dielectric constant than the first insulating film.
    Type: Application
    Filed: July 16, 2018
    Publication date: November 29, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Shirou OZAKI, NAOYA OKAMOTO
  • Patent number: 10084059
    Abstract: A semiconductor device includes a first semiconductor layer formed of a nitride semiconductor, on a substrate; a second semiconductor layer formed of a nitride semiconductor, on the first semiconductor layer; a source electrode and a drain electrode formed on the second semiconductor layer; a first insulating film formed on the second semiconductor layer; a second insulating film formed on the first insulating film; and a gate electrode formed on the second insulating film. The first insulating film includes a nitride film formed on a side of the second semiconductor layer, and an oxynitride film formed on the nitride film, and the second insulating film is formed of an oxide.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: September 25, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Naoya Okamoto
  • Patent number: 10056460
    Abstract: A semiconductor device includes: a semiconductor layer; a first insulating film which covers a surface of the semiconductor layer; a first adhering film which is formed on a surface of the first insulating film and contains a carbonyl group; and a second insulating film which covers a surface of the first adhering film and has a lower dielectric constant than the first insulating film.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: August 21, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Naoya Okamoto
  • Patent number: 10043897
    Abstract: A method of fabricating a semiconductor device may form a nitride semiconductor layer on a substrate, form a first insulator layer on the nitride semiconductor layer by steam oxidation of ALD, form a second insulator layer on the first insulator layer by oxygen plasma oxidation of ALD, form a gate electrode on the second insulator layer, and form a source and drain electrodes on the nitride semiconductor layer. The nitride semiconductor layer may include a first semiconductor layer on the substrate, and a second semiconductor layer on the first semiconductor layer.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: August 7, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Shirou Ozaki
  • Patent number: 10043727
    Abstract: A compound semiconductor device includes a first protection film which covers a surface of a compound semiconductor layer, where the first protection film is an insulating film whose major constituent is Si and at least one element between N and O, and a hydrophobic layer containing Si—CxHy is formed at a surface thereof.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: August 7, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Naoya Okamoto
  • Publication number: 20180197979
    Abstract: A semiconductor device includes a semiconductor stacked structure in which a semiconductor layer including an electron supply layer and an electron transit layer is stacked, and a gate electrode contacting with the semiconductor layer included in the semiconductor stacked structure or an insulating layer. The portion of the gate electrode contacting with the semiconductor layer or the insulating layer is an oxide of a metal configuring the portion of the gate electrode contacting with the semiconductor layer or the insulating layer.
    Type: Application
    Filed: March 5, 2018
    Publication date: July 12, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Shirou OZAKI, Kozo Makiyama, NAOYA OKAMOTO
  • Publication number: 20180182854
    Abstract: A semiconductor device includes a compound semiconductor layer, a gate electrode, and first and second insulating layers. The first insulating layer covers the gate electrode on the compound semiconductor layer and has a cavity that surrounds the gate electrode. The second insulating layer is provided on the first insulating layer and has an opening at a position corresponding to the cavity. A part of the second insulating layer, which is provided on the first insulating layer that covers the gate electrode, corresponding to the cavity is removed via the opening, so that the generation of parasitic capacitance due to the second insulating layer is suppressed.
    Type: Application
    Filed: October 31, 2017
    Publication date: June 28, 2018
    Applicant: FUJITSU LIMITED
    Inventor: Shirou OZAKI
  • Patent number: 10002942
    Abstract: A semiconductor device includes a first semiconductor layer made of a nitride semiconductor and formed on a substrate, a second semiconductor layer made of a material including InAlN and formed on the first semiconductor layer, an insulator layer formed by an oxidized surface part of the second semiconductor layer, a gate electrode formed on the insulator layer, and a source electrode and a drain electrode respectively formed on the first or second semiconductor layer.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: June 19, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Kozo Makiyama, Shirou Ozaki
  • Patent number: 9966463
    Abstract: A method of producing a semiconductor device includes forming an insulating film on a substrate on which a semiconductor layer is formed; removing a part of the insulating film by etching to form an opening in the insulating film; supplying steam with a temperature greater than or equal to 200° C. and less than or equal to 600° C. to the opening formed in the insulating film; after supplying the steam, applying a solution including a silicon compound to a side surface of the insulating film defining the opening; and forming a hydrophobic film on the side surface of the insulating film defining the opening by polymerizing the silicon compound.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: May 8, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Naoya Okamoto
  • Patent number: 9941401
    Abstract: A semiconductor device includes a semiconductor stacked structure in which a semiconductor layer including an electron supply layer and an electron transit layer is stacked, and a gate electrode contacting with the semiconductor layer included in the semiconductor stacked structure or an insulating layer. The portion of the gate electrode contacting with the semiconductor layer or the insulating layer is an oxide of a metal configuring the portion of the gate electrode contacting with the semiconductor layer or the insulating layer.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: April 10, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Kozo Makiyama, Naoya Okamoto
  • Publication number: 20180090595
    Abstract: A semiconductor device includes a first semiconductor layer formed of a compound semiconductor, provided over a substrate; a second semiconductor layer formed of a compound semiconductor including In and Al, provided over the first semiconductor layer; source and drain electrodes provided on the second semiconductor layer; and a gate electrode provided between the source and drain electrodes, on the second semiconductor layer. The compound semiconductor in the second semiconductor layer has a first In composition ratio in a region on a side facing the substrate and a second In composition ratio in a region on an opposite side, the second In composition ratio being lower than the first In composition ratio, and the source and drain electrodes are provided in contact with the region having the first In composition ratio, and the gate electrode is provided on the region having the second In composition ratio.
    Type: Application
    Filed: July 18, 2017
    Publication date: March 29, 2018
    Applicant: FUJITSU LIMITED
    Inventor: Shirou OZAKI