Abstract: Disclosed is technology for selectively determining whether to duplicate a packet based on factors beyond just the application it is associated with. For example, some methods determine a criticality of the packet by reading a tag stored in a header of the packet. The tag can represent a group to which the user is associated with, e.g., the financial department, and assign a criticality score based on that group and in some cases other factors. The criticality score can be measured against a threshold to determine whether duplication should occur in the next hop. The method therefore selectively determines whether to duplicate a packet, thereby avoiding costly overduplication, while also placing this tag in a header of the packet, which can be read easily and without deep packet inspection.

Abstract: A computer-implemented system can implement a temporal and context-based transformer for improved communication protocol selection across disparate networks. The system can train a transformer-based neural network using embeddings generated separately from, respectively, profile attributes, channel-specific behaviors, external clinical events and/or observed outcomes. The transformer-based neural network can be trained to reconstruct masked events and inter-event time gaps, then fine-tuned with a dual-loss objective that simultaneously preserves behavioral grammar and maximizes outcome prediction accuracy. During live operation the model ingests current profile, real-time telemetry and new contextual events to temporally and contextually select communication channels to generate events across disparate networks.

Abstract: An intelligent forward error correction (iFEC) method and system are automatically triggered and started for providing forward error correction for applications when packet loss is predicted to be more than a threshold packet loss level during a prescribed interval and the actual packet loss is more than a threshold level. Similarly, the intelligent FEC method and system may be automatically disabled when packet loss is predicted to be less than the threshold level during a prescribed interval. If prescribed bandwidth of a transmission uplink through which application data packets will pass will be slowed or choked by use of iFEC, then iFEC may be disabled or stopped to prevent further congestion in the uplink. That is, according to examples, iFEC is started and stopped based on predicted packet loss and uplink/bandwidth health as opposed to simply operating forward error correction in a “always on” or manually provisioned manner.

Abstract: An intelligent forward error correction (iFEC) method and system are automatically triggered and started for providing forward error correction for applications when packet loss is predicted to be more than a threshold packet loss level during a prescribed interval and the actual packet loss is more than a threshold level. Similarly, the intelligent FEC method and system may be automatically disabled when packet loss is predicted to be less than the threshold level during a prescribed interval. If prescribed bandwidth of a transmission uplink through which application data packets will pass will be slowed or choked by use of iFEC, then iFEC may be disabled or stopped to prevent further congestion in the uplink. That is, according to examples, iFEC is started and stopped based on predicted packet loss and uplink/bandwidth health as opposed to simply operating forward error correction in a “always on” or manually provisioned manner.

Abstract: An integrated circuit device includes a processing element, a plurality of memory controllers, and a network on chip (NoC). The NoC has a first network including a plurality of interconnected switches having routing tables and a second network coupled to the first network. The second network includes a crossbar. The NoC is configured to implement a path coupling the processing element and the plurality of memory controllers in which a first portion of the path is implemented in the first network and a second portion of the path is implemented in the second network. The crossbar connects the processing element to any memory controller of the plurality of memory controllers while maintaining a same delay for the path.

Abstract: An example is a circuit. The circuit includes a memory array, a mimic column, a mimic resistor, and a calibration circuit. The mimic column is along a periphery of the memory array. The mimic resistor is in a path through the mimic column. The calibration circuit is configured to calibrate a voltage for writing a memory cell in the memory array. The calibration circuit is electrically connected to the mimic resistor. A voltage may be calibrated, such as by the calibration circuit, using the mimic column. A value may be written to a memory cell of the memory array using the calibrated voltage.

Abstract: A memory device includes a plurality of select lines, a plurality of word lines, an array of memory cells, a bitline, and a resistance device. The array of memory cells includes multiple rows and multiple columns. The bitline is structured to receive a current in a read operation, causing a value stored in a selected memory cell to be readable when a select line and a word line that interest the selected memory cell are selected. The resistance device has a first terminal and a second terminal. The first terminal is coupled to the select lines, and the second terminal is coupled to ground. The resistance device is structured to bias, in the read operation, word lines of unselected memory cells in a column of a selected memory cell to a determined negative voltage.

Abstract: A system includes a plurality of processing elements and a plurality of memory controllers. The system includes a network on chip (NoC) providing connectivity between the plurality of processing elements and the plurality of memory controllers. The NoC includes a sparse network coupled to the plurality of processing elements and a non-blocking network coupled to the sparse network and the plurality of memory controllers. The plurality of processing elements execute a plurality of applications. Each application has a same deterministic memory access performance in accessing associated ones of the plurality of memory controllers via the sparse network and the non-blocking network of the NoC.

Abstract: A memory device includes clock signal generation circuitry, and first integrated level shifter and latch circuitry. The clock signal generation circuitry receives a first clock signal and an isolation signal, and generates a second clock signal based on the first clock signal and the isolation signal. The isolation signal corresponds to a power state of a power supply associated with the first clock signal. The first integrated level shifter and latch circuitry receives an input signal in a first power supply domain, and latches a value the input signal based on the second clock signal. Further, the first integrated level shifter and latch circuitry outputs, based on the latched value, an output signal in a second power supply domain different than the first power supply domain.

Abstract: A delay circuit. In some embodiments, a non-transitory computer readable medium includes stored instructions, which when executed by a processor, cause the processor to generate a digital representation of a circuit including: a first inverter, having an input, an output, and two power supply connections; a first current source, electrically coupled in series between a power supply conductor and a power supply connection of the two power supply connections of the first inverter; and a ramp generator circuit, electrically coupled to the input of the first inverter.

Abstract: A memory device includes bitcells connected to wordlines and bitlines, and driver circuitry that updates the bitcells. The driver circuitry includes first transistors, and a first inverter device. The first transistors drive a bitcell of a memory device. The first inverter device is coupled to the first transistors, and drives the first transistors with a first control signal. The first inverter device includes first inverter circuitry and second inverter circuitry. The first inverter circuitry receives a first signal, a first voltage, and a second voltage differing from the first voltage, and generates a first inverted signal based on the first signal, the first voltage and the second voltage. The second inverter circuitry receives the first inverted signal, the second voltage and a third voltage differing from the second voltage, and generates the first control signal based on the first inverted signal, the third voltage and the second voltage.

Abstract: A method of using on-chip circuitry to test a memory of a chip is provided. The method including, in a capture stage, receiving, at a first n-bit compression structure including n first stage latches corresponding to each bit of the first n-bit compression structure, a value at each respective first stage latch for each of n memory addresses of the memory, such that each respective first stage latch receives a respective value from a memory address of the memory, n being an integer greater than one, and in the capture stage, passing the values from each respective first stage latch through compression logic of the first n-bit compression structure to output a single compressed address value, providing the single compressed address value to a second stage latch of the first n-bit compression structure.

Abstract: Tracking circuitry for a memory device is disclosed. The tracking circuitry includes an inverter, a level shifter, delay circuitry, and a logic gate. The inverter is configured to receive a first clock signal and generate an inverted clock signal. The level shifter is configured to receive the first clock signal and the inverted clock signal and generate a level shifted clock signal. The delay circuitry is configured to receive the level shifted clock signal and generate an inverted level shifted clock signal. The logic gate comprises a first input configured to receive the first clock signal and a second input configured to receive the inverted level shifted clock signal. The logic gate is configured to generate a second clock signal based on the first clock signal and the inverted level shifted clock signal.

Abstract: A system includes a plurality of processing elements and a plurality of memory controllers. The system includes a network on chip (NoC) providing connectivity between the plurality of processing elements and the plurality of memory controllers. The NoC includes a sparse network coupled to the plurality of processing elements and a non-blocking network coupled to the sparse network and the plurality of memory controllers. The plurality of processing elements execute a plurality of applications. Each application has a same deterministic memory access performance in accessing associated ones of the plurality of memory controllers via the sparse network and the non-blocking network of the NoC.

Abstract: Some examples described herein provide a buffer memory pool circuitry that comprises a plurality of buffer memory circuits that store an entry identifier, a payload portion, and a next-entry pointer. The buffer memory pool circuitry further comprises a processor configured to identify an allocation request for a first virtual channel associated with a sequence of buffer memory circuits and comprising a start pointer identifying an initial buffer memory circuit. The processor is further configured to program the first virtual channel circuit based on setting the start pointer for the first virtual channel circuit to be equal to the entry identifier of the initial buffer memory circuit. The processor is also configured to monitor usage. A length of the sequence of buffer memory circuits of the first virtual channel circuit is defined by a start pointer for a second virtual channel circuit subsequent to the first virtual channel circuit.

Abstract: A memory device includes a plurality of select lines, a plurality of word lines, an array of memory cells, a bitline, and a resistance device. The array of memory cells includes multiple rows and multiple columns. The bitline is structured to receive a current in a read operation, causing a value stored in a selected memory cell to be readable when a select line and a word line that interest the selected memory cell are selected. The resistance device has a first terminal and a second terminal. The first terminal is coupled to the select lines, and the second terminal is coupled to ground. The resistance device is structured to bias, in the read operation, word lines of unselected memory cells in a column of a selected memory cell to a determined negative voltage.

Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.

Abstract: A memory device includes bitcells connected to wordlines and bitlines, and driver circuitry that updates the bitcells. The driver circuitry includes first transistors, and a first inverter device. The first transistors drive a bitcell of a memory device. The first inverter device is coupled to the first transistors, and drives the first transistors with a first control signal. The first inverter device includes first inverter circuitry and second inverter circuitry. The first inverter circuitry receives a first signal, a first voltage, and a second voltage differing from the first voltage, and generates a first inverted signal based on the first signal, the first voltage and the second voltage. The second inverter circuitry receives the first inverted signal, the second voltage and a third voltage differing from the second voltage, and generates the first control signal based on the first inverted signal, the third voltage and the second voltage.

Abstract: A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.

Abstract: A memory device includes clock signal generation circuitry, and first integrated level shifter and latch circuitry. The clock signal generation circuitry receives a first clock signal and an isolation signal, and generates a second clock signal based on the first clock signal and the isolation signal. The isolation signal corresponds to a power state of a power supply associated with the first clock signal. The first integrated level shifter and latch circuitry receives an input signal in a first power supply domain, and latches a value the input signal based on the second clock signal. Further, the first integrated level shifter and latch circuitry outputs, based on the latched value, an output signal in a second power supply domain different than the first power supply domain.