Abstract: A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.

Abstract: An online concierge system allows users to order items from a warehouse having multiple physical locations, allowing a user to order items at any given warehouse location. To select a warehouse location for a warehouse selected by a user, the online concierge system identifies a set of items that the user has a threshold likelihood of purchasing from prior orders by the user. For each of a set of warehouse locations, the online concierge system applies a machine-learned item availability model to each item of the identified set. From the availabilities of items of the set at each warehouse location of the set, the online concierge system selects a warehouse location. The online concierge system identifies an inventory of items from the selected warehouse location to the user for inclusion in an order.

Abstract: A memory device includes clock signal generation circuitry, and first integrated level shifter and latch circuitry. The clock signal generation circuitry receives a first clock signal and an isolation signal, and generates a second clock signal based on the first clock signal and the isolation signal. The isolation signal corresponds to a power state of a power supply associated with the first clock signal. The first integrated level shifter and latch circuitry receives an input signal in a first power supply domain, and latches a value the input signal based on the second clock signal. Further, the first integrated level shifter and latch circuitry outputs, based on the latched value, an output signal in a second power supply domain different than the first power supply domain.

Abstract: An online concierge system maintains a taxonomy associating one or more specific items offered by a warehouse with a category. When the online concierge system receives a selection of an item from a user for inclusion in an order, the online concierge system determines a category including the selected item. From prior received orders, the online concierge system 102 identifies additional categories including one or more items included in various prior received orders. Based on cooccurrences of the category and the additional categories, the online concierge system generates scores for the additional categories. An additional category is selected based on the scores and specific items from the selected additional category are displayed via an interface for selection by the user.

Abstract: An online concierge system may determine recommended search terms for a user. The online concierge system may receive a request from a user to view a user interface configured to receive a search query. The online concierge system retrieves long-term activity data including previous search terms entered by the user while searching for items to add to an online shopping cart. For each previous search term, the online concierge system retrieves categorical search terms corresponding to one or more categories to which the previous search term was mapped. The online concierge system determines a set of nearby categorical search terms and sends, for display via a client device, the set of nearby categorical search terms as recommended search terms.

Abstract: Tracking circuitry for a memory device is disclosed. The tracking circuitry includes an inverter, a level shifter, delay circuitry, and a logic gate. The inverter is configured to receive a first clock signal and generate an inverted clock signal. The level shifter is configured to receive the first clock signal and the inverted clock signal and generate a level shifted clock signal. The delay circuitry is configured to receive the level shifted clock signal and generate an inverted level shifted clock signal. The logic gate comprises a first input configured to receive the first clock signal and a second input configured to receive the inverted level shifted clock signal. The logic gate is configured to generate a second clock signal based on the first clock signal and the inverted level shifted clock signal.

Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.

Abstract: An online concierge shopping system identifies candidate items to a user for inclusion in an order based on prior user inclusion of items in orders and items currently included in the order. From a multi-dimensional tensor generated from cooccurrences of items in orders from various users, the online concierge system generates item embeddings and user embeddings in a common latent space by decomposing the multi-dimensional tensor. From items included in an order, the online concierge system generates an order embedding from item embeddings of the items included in the order. Scores for candidate items are determined based on similarity of item embeddings for the candidate items to the order embedding. Candidate items are selected based on their scores, with the selected candidate items identified to the user.

Abstract: Some examples described herein provide a buffer memory pool circuitry that comprises a plurality of buffer memory circuits that store an entry identifier, a payload portion, and a next-entry pointer. The buffer memory pool circuitry further comprises a processor configured to identify an allocation request for a first virtual channel associated with a sequence of buffer memory circuits and comprising a start pointer identifying an initial buffer memory circuit. The processor is further configured to program the first virtual channel circuit based on setting the start pointer for the first virtual channel circuit to be equal to the entry identifier of the initial buffer memory circuit. The processor is also configured to monitor usage. A length of the sequence of buffer memory circuits of the first virtual channel circuit is defined by a start pointer for a second virtual channel circuit subsequent to the first virtual channel circuit.

Abstract: An online concierge system may determine recommended search terms for a user. The online concierge system may receive a request from a user to view a user interface configured to receive a search query. The online concierge system retrieves long-term activity data including previous search terms entered by the user while searching for items to add to an online shopping cart. For each previous search term, the online concierge system retrieves categorical search terms corresponding to one or more categories to which the previous search term was mapped. The online concierge system determines a set of nearby categorical search terms and sends, for display via a client device, the set of nearby categorical search terms as recommended search terms.

Abstract: A method of using on-chip circuitry to test a memory of a chip is provided. The method including, in a capture stage, receiving, at a first n-bit compression structure including n first stage latches corresponding to each bit of the first n-bit compression structure, a value at each respective first stage latch for each of n memory addresses of the memory, such that each respective first stage latch receives a respective value from a memory address of the memory, n being an integer greater than one, and in the capture stage, passing the values from each respective first stage latch through compression logic of the first n-bit compression structure to output a single compressed address value, providing the single compressed address value to a second stage latch of the first n-bit compression structure.

Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.

Abstract: A method comprises collecting data corresponding to a plurality of components in a system, wherein the data comprises information about at least one of respective protocols and respective interfaces associated with respective ones of the plurality of components. The data is analyzed to determine at least one of the respective protocols and the respective interfaces associated with the respective ones of the plurality of components. In the method, operations of one or more components of the plurality of components are tested based at least in part on the determination of the at least one of the respective protocols and the respective interfaces. The method further includes outputting respective statuses of the one or more components, wherein the respective statuses are derived at least in part from the testing.

Abstract: A row decoder located on one side of a memory array selectively drives word lines in response to a row address. A word line fault detection circuit located on an opposite side of the first memory array operates to detect an open word line fault between the opposed sides of the memory array. The word line fault detection circuit includes a first clamp circuit that operates to clamp the word lines to ground. An encoder circuit encodes signals on the word lines to generate an encoded address. The encoded address is compared to the row address by a comparator circuit which sets an error flag indicating the open word line fault has been detected if the encoded address does not match the row address.

Abstract: A method comprises collecting data corresponding to a plurality of components in a system, wherein the data comprises information about one or more issues with the plurality of components. The data is analyzed and categorized based at least in part on the analysis. In the method, one or more application programming interfaces (APIs) are selected to monitor respective statuses of the plurality of components, wherein the selection is based at least in part on the categorization of the data, and the data is pushed to the one or more APIs.

Abstract: A method comprises collecting data corresponding to a plurality of components in a system, wherein the data comprises information about one or more issues with the plurality of components. The data is analyzed and categorized based at least in part on the analysis. In the method, one or more application programming interfaces (APIs) are selected to monitor respective statuses of the plurality of components, wherein the selection is based at least in part on the categorization of the data, and the data is pushed to the one or more APIs.

Abstract: An online concierge system allows users to order items from a warehouse having multiple physical locations, allowing a user to order items at any given warehouse location. To select a warehouse location for a warehouse selected by a user, the online concierge system identifies a set of items that the user has a threshold likelihood of purchasing from prior orders by the user. For each of a set of warehouse locations, the online concierge system applies a machine-learned item availability model to each item of the identified set. From the availabilities of items of the set at each warehouse location of the set, the online concierge system selects a warehouse location. The online concierge system identifies an inventory of items from the selected warehouse location to the user for inclusion in an order.

Abstract: A method comprises receiving a request for validation of software comprising one or more applications, analyzing the request and generating one or more validation steps based at least in part on the analysis. In the method, a time to complete the one or more validation steps is predicted. The predicting is performed using one or more machine learning models, and is based at least in part on a type and a number of the one or more applications.

Abstract: An online concierge system accesses a hierarchical taxonomy of products each labeled with a category of the hierarchical taxonomy. The online concierge system receives, from an inventory database, an unlabeled product, which not included in the hierarchical taxonomy. The online concierge system inputs the unlabeled product to a replacement model. The replacement model is trained to output, for each of one or more labeled products from the hierarchical taxonomy, a likelihood that a user would select the labeled product as a replacement for an input product. The online concierge system selects a labeled product from the one or more labeled products based on the likelihoods. The online concierge system adds the unlabeled product to a category of the hierarchical taxonomy based on the selected labeled product.

Abstract: First and second memory arrays have common word lines driven by a row decoder in response to a row address. A first word line encoder associated with the first memory array encodes signals on the word lines to generate a first encoded value, and a second word line encoder associated with the second memory array encodes signals on the word lines to generate a second encoded value. Comparison circuitry compares the first encoded value to a first expected value (e.g., a first portion of the row address) and compares the second encoded value to a second expected value (e.g., a second portion of the row address). An error flag is asserted to indicate presence of a word line fault based upon a lack of match between the first encoded value and the first expected value and/or a lack of match between the second encoded value and the second expected value.