Patents by Inventor Shishir Kumar

Shishir Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170235717
    Abstract: The present disclosure relates to a method and unit for building semantic rule for a semantic data which includes initially receiving one or more actions performed by a user on a visualization user interface associated with a semantic rule building unit. Upon receiving, the one or more actions are processed to determine a plurality of clauses comprising at least antecedent clauses and consequent clauses associated with the semantic rule. Further, a sequence associated with the plurality of clauses is determined based on the one or more actions. The semantic rule for the semantic data is generated based on the determined sequence.
    Type: Application
    Filed: March 28, 2016
    Publication date: August 17, 2017
    Inventor: Shishir KUMAR
  • Patent number: 9648537
    Abstract: A device and method for profile switching based on location and wireless network quality are provided. A client device determines relevant locations for a user of the client device based on a variety of factors. After determining that a location is of particular relevance to the user, the client device will proceed to collect wireless network parameters for each available wireless network at each of the relevant locations for the user. The client device then determines a quality score for each wireless network at each relevant location and proceeds to utilize the quality score to make wireless network profile switching decisions as the client device travels between the relevant locations.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: May 9, 2017
    Assignee: Google Inc.
    Inventors: Weihua Tan, Shishir Kumar Agrawal
  • Patent number: 9590602
    Abstract: According to an embodiment, a method of generating a clock pulse includes receiving a leading edge at a clock input at a time when an enable signal is active, generating an edge at a clock output based on the received leading edge at the clock input, latching a logic value corresponding to the edge at the clock output, preventing changes at the clock input from affecting the latched logic value after the logic value is latched, resetting the latched logic value after a first delay time, and maintaining the reset logic value until a second edge is received at the clock input. The second edge at the clock input matches the leading edge at the clock input.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: March 7, 2017
    Assignee: STMicroelectronics International N.V.
    Inventors: Shishir Kumar, Tanmoy Roy
  • Patent number: 9584579
    Abstract: A method and system for providing page visibility information are provided herein. Aspects of this disclosure provide an interface by which a browser may make the visibility state of a particular page available to the page itself. The browser may track the visibility state of the page as it changes and store the state in a variable associated with the page. Code executing within the page may query this variable to determine the visibility state and take appropriate action. The browser may provide an application programming interface (API) to allow the page to request the visibility state.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: February 28, 2017
    Assignee: Google Inc.
    Inventors: Shishir Kumar Agrawal, John Alexander Komoroske
  • Publication number: 20170032025
    Abstract: This disclosure relates generally to information retrieval, and more particularly to a system and method for verifiable query of semantic data. In one embodiment, a method is provided for performing verifiable query on semantic data. The method comprises rendering a visualization of an ontology of the semantic data, acquiring one or more user interactions with the visualization, generating a semantic query and a natural language interpretation based on the one or more user interactions, and presenting the semantic query and the natural language interpretation to a user for validation.
    Type: Application
    Filed: September 21, 2015
    Publication date: February 2, 2017
    Inventor: Shishir KUMAR
  • Publication number: 20160345145
    Abstract: In one implementation, a computer-implemented method includes: receiving, at a computer system, a multimedia message service (MMS) message for delivery to a client computing device; storing, by the computer system, the MMS message; generating, by the computer system, a traditional short message service (SMS) message including a notification that the MMS message is available for download from the computer system; transmitting, by the computer system, the SMS message to the client computing device; receiving, after transmitting the SMS message, a request from the client computing device to download the MMS message; and sending, by the computer system, the MMS message to the client computing device.
    Type: Application
    Filed: May 20, 2016
    Publication date: November 24, 2016
    Inventors: Andrew Rowny, Shishir Kumar Agrawal, Ji Yang, Cheuksan Edward Wang, Abhijith Shastry
  • Publication number: 20160315900
    Abstract: In one implementation, a computer-implemented method, includes receiving, at a computer system, a message for delivery to a client computing device; determining, by the computer system, a unique identifier for the message; generating an identified message that includes the message and at least a portion of the unique identifier; and sending, by the computer system and to the client computing device, the identified message over a first communication channel and a second communication channel, wherein the first communication channel is different from the second communication channel.
    Type: Application
    Filed: April 21, 2016
    Publication date: October 27, 2016
    Inventors: Andrew Rowny, Shishir Kumar Agrawal
  • Publication number: 20160316410
    Abstract: A device and method for profile switching based on location and wireless network quality are provided. A client device determines relevant locations for a user of the client device based on a variety of factors. After determining that a location is of particular relevance to the user, the client device will proceed to collect wireless network parameters for each available wireless network at each of the relevant locations for the user. The client device then determines a quality score for each wireless network at each relevant location and proceeds to utilize the quality score to make wireless network profile switching decisions as the client device travels between the relevant locations.
    Type: Application
    Filed: April 17, 2015
    Publication date: October 27, 2016
    Inventors: Weihua TAN, Shishir Kumar AGRAWAL
  • Patent number: 9324414
    Abstract: A write is performed to a first cell of a memory at a first row and column during a first memory access cycle. A memory access operation is made to a second cell at a second row and column during an immediately following second memory access cycle. If the memory access is a read from the second cell and the second row is the same as the first row, or if the memory access is a write to the second cell and the second row is the same as the first row and the second column is different than the first column, then a simultaneous operation is performed during the second memory access cycle. The simultaneous operation is an access of the second cell (for read or write) and a re-write of data from the first memory access cycle write operation back to the first cell.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: April 26, 2016
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Nishu Kohli, Shishir Kumar
  • Publication number: 20160048688
    Abstract: Systems and techniques are provided for restricting system calls using protected storage. A system call to a restricted system component may be received from an application. The application may be determined to have permission to make the system call to the restricted system component. A signature associated with the application may be verified using a public key from a protected storage. The public key may be sent to the protected storage by a computing device of a party authorized to modify data in the protected storage. The restricted system component may be permitted to perform a function indicated by the system call when the public key successfully verifies the signature associated with application.
    Type: Application
    Filed: August 14, 2014
    Publication date: February 18, 2016
    Inventors: Andrew Flynn, Shishir Kumar Agrawal, Simon Arscott, Lawrence Jonathan Brunsman
  • Publication number: 20160019250
    Abstract: According to an exemplary embodiment, a method for generating an enterprise user group is provided. The method may include receiving a set of attributes for an enterprise network user; receiving one or more enterprise group member identification rules including a similarity distance threshold and a set of target attributes; calculating, using a hardware processor, a similarity assessment score based on the set of target attributes and the set of attributes; and determining, using the hardware processor, whether the enterprise network user is an enterprise group member based on the similarity assessment score and the similarity distance threshold.
    Type: Application
    Filed: September 5, 2014
    Publication date: January 21, 2016
    Applicant: Wipro Limited
    Inventors: Shishir Kumar, Jayakumar Panicker
  • Publication number: 20150365080
    Abstract: According to an embodiment, a method of generating a clock pulse includes receiving a leading edge at a clock input at a time when an enable signal is active, generating an edge at a clock output based on the received leading edge at the clock input, latching a logic value corresponding to the edge at the clock output, preventing changes at the clock input from affecting the latched logic value after the logic value is latched, resetting the latched logic value after a first delay time, and maintaining the reset logic value until a second edge is received at the clock input. The second edge at the clock input matches the leading edge at the clock input.
    Type: Application
    Filed: June 13, 2014
    Publication date: December 17, 2015
    Inventors: Shishir Kumar, Tanmoy Roy
  • Patent number: 9165642
    Abstract: A memory cell includes a latch having a true data node and a complement data node, a true bitline, a complement bitline, a first access transistor coupled between the true bitline and the true data node, and a second access transistor coupled between the complement bitline and the complement data node. A wordline driver circuit includes a true wordline coupled to control the first access transistor and a complement wordline coupled to control the second access transistor. The wordline driver generates control signals on the true and complement wordlines to access the memory cell by: actuating the first access transistor while the second access transistor is not actuated and then actuating the second access transistor while the first access transistor is not actuated. The bitlines and wordlines are supplied from different sets of power supply voltages, with the bitline high supply voltage being less than the wordline high supply voltage.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: October 20, 2015
    Assignee: STMicroelectronics International N.V.
    Inventor: Shishir Kumar
  • Patent number: 9147453
    Abstract: Delays are introduced in self-timed memories by introducing a capacitance on the path of a signal to be delayed. The capacitances are realized by using idle-lying metal layers in the circuitry. The signal to be delayed is connected to the idle-lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal, which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since idle-lying metal capacitances are utilized, the circuitry can be implemented using a minimum amount of additional hardware. Also, the delay provided by the circuitry is a function of memory cell SPICE characteristics and core parasitic capacitances.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: September 29, 2015
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Nishu Kohli, Mudit Bhargava, Shishir Kumar
  • Publication number: 20150269262
    Abstract: A method for retrieving information includes determining, by the information retrieval management computing device, when an identified subject of interest in a received query maps to one of one or more ontology entities. An identification is made, by the information retrieval management computing device, when the identified subject of interest is one of one or more existing subjects of interest when the identified subject of interest is determined to map to one of the ontology entities. One or more filters associated with the identified subject of interest are stored by the information retrieval management computing device.
    Type: Application
    Filed: May 6, 2014
    Publication date: September 24, 2015
    Applicant: Wipro Limited
    Inventor: Shishir Kumar
  • Publication number: 20150195156
    Abstract: A method and system for providing page visibility information are provided herein. Aspects of this disclosure provide an interface by which a browser may make the visibility state of a particular page available to the page itself. The browser may track the visibility state of the page as it changes and store the state in a variable associated with the page. Code executing within the page may query this variable to determine the visibility state and take appropriate action. The browser may provide an application programming interface (API) to allow the page to request the visibility state.
    Type: Application
    Filed: December 1, 2011
    Publication date: July 9, 2015
    Applicant: GOOGLE INC.
    Inventors: Shishir Kumar Agrawal, John Alexander Komoroske
  • Patent number: 9006841
    Abstract: A dual port SRAM has two data storage nodes, a true data and complementary data. A first pull down transistor has an active area that forms the drain region of the first transistor and the true data storage node that is physically isolated from all other transistor active areas of the memory cell. A second pull down transistor has an active area that forms the drain region of a second transistor that is the complementary data node that is physically isolated from all other transistor active areas of the memory cell.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: April 14, 2015
    Assignee: STMicroelectronics International N.V.
    Inventors: Shishir Kumar, Dibya Dipti, Pierre Malinge
  • Publication number: 20150055400
    Abstract: Delays are introduced in self-timed memories by introducing a capacitance on the path of a signal to be delayed. The capacitances are realized by using idle-lying metal layers in the circuitry. The signal to be delayed is connected to the idle-lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal, which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since idle-lying metal capacitances are utilized, the circuitry can be implemented using a minimum amount of additional hardware. Also, the delay provided by the circuitry is a function of memory cell SPICE characteristics and core parasitic capacitances.
    Type: Application
    Filed: November 4, 2014
    Publication date: February 26, 2015
    Inventors: NISHU KOHLI, MUDIT BHARGAVA, SHISHIR KUMAR
  • Patent number: 8963053
    Abstract: Delays are introduced in self-timed memories by introducing a capacitance on the path of a signal to be delayed. The capacitances are realized by using idle-lying metal layers in the circuitry. The signal to be delayed is connected to the idle-lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal, which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since idle-lying metal capacitances are utilized, the circuitry can be implemented using a minimum amount of additional hardware. Also, the delay provided by the circuitry is a function of memory cell SPICE characteristics and core parasitic capacitances.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: February 24, 2015
    Assignee: STMicroelectronics PVT. Ltd.
    Inventors: Nishu Kohli, Mudit Bhargava, Shishir Kumar
  • Publication number: 20150029795
    Abstract: A write is performed to a first cell of a memory at a first row and column during a first memory access cycle. A memory access operation is made to a second cell at a second row and column during an immediately following second memory access cycle. If the memory access is a read from the second cell and the second row is the same as the first row, or if the memory access is a write to the second cell and the second row is the same as the first row and the second column is different than the first column, then a simultaneous operation is performed during the second memory access cycle. The simultaneous operation is an access of the second cell (for read or write) and a re-write of data from the first memory access cycle write operation back to the first cell.
    Type: Application
    Filed: July 24, 2013
    Publication date: January 29, 2015
    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Nishu Kohli, Shishir Kumar