Patents by Inventor Shishir Kumar
Shishir Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160019250Abstract: According to an exemplary embodiment, a method for generating an enterprise user group is provided. The method may include receiving a set of attributes for an enterprise network user; receiving one or more enterprise group member identification rules including a similarity distance threshold and a set of target attributes; calculating, using a hardware processor, a similarity assessment score based on the set of target attributes and the set of attributes; and determining, using the hardware processor, whether the enterprise network user is an enterprise group member based on the similarity assessment score and the similarity distance threshold.Type: ApplicationFiled: September 5, 2014Publication date: January 21, 2016Applicant: Wipro LimitedInventors: Shishir Kumar, Jayakumar Panicker
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Publication number: 20150365080Abstract: According to an embodiment, a method of generating a clock pulse includes receiving a leading edge at a clock input at a time when an enable signal is active, generating an edge at a clock output based on the received leading edge at the clock input, latching a logic value corresponding to the edge at the clock output, preventing changes at the clock input from affecting the latched logic value after the logic value is latched, resetting the latched logic value after a first delay time, and maintaining the reset logic value until a second edge is received at the clock input. The second edge at the clock input matches the leading edge at the clock input.Type: ApplicationFiled: June 13, 2014Publication date: December 17, 2015Inventors: Shishir Kumar, Tanmoy Roy
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Patent number: 9165642Abstract: A memory cell includes a latch having a true data node and a complement data node, a true bitline, a complement bitline, a first access transistor coupled between the true bitline and the true data node, and a second access transistor coupled between the complement bitline and the complement data node. A wordline driver circuit includes a true wordline coupled to control the first access transistor and a complement wordline coupled to control the second access transistor. The wordline driver generates control signals on the true and complement wordlines to access the memory cell by: actuating the first access transistor while the second access transistor is not actuated and then actuating the second access transistor while the first access transistor is not actuated. The bitlines and wordlines are supplied from different sets of power supply voltages, with the bitline high supply voltage being less than the wordline high supply voltage.Type: GrantFiled: January 22, 2013Date of Patent: October 20, 2015Assignee: STMicroelectronics International N.V.Inventor: Shishir Kumar
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Patent number: 9147453Abstract: Delays are introduced in self-timed memories by introducing a capacitance on the path of a signal to be delayed. The capacitances are realized by using idle-lying metal layers in the circuitry. The signal to be delayed is connected to the idle-lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal, which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since idle-lying metal capacitances are utilized, the circuitry can be implemented using a minimum amount of additional hardware. Also, the delay provided by the circuitry is a function of memory cell SPICE characteristics and core parasitic capacitances.Type: GrantFiled: November 4, 2014Date of Patent: September 29, 2015Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Nishu Kohli, Mudit Bhargava, Shishir Kumar
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Publication number: 20150269262Abstract: A method for retrieving information includes determining, by the information retrieval management computing device, when an identified subject of interest in a received query maps to one of one or more ontology entities. An identification is made, by the information retrieval management computing device, when the identified subject of interest is one of one or more existing subjects of interest when the identified subject of interest is determined to map to one of the ontology entities. One or more filters associated with the identified subject of interest are stored by the information retrieval management computing device.Type: ApplicationFiled: May 6, 2014Publication date: September 24, 2015Applicant: Wipro LimitedInventor: Shishir Kumar
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Publication number: 20150195156Abstract: A method and system for providing page visibility information are provided herein. Aspects of this disclosure provide an interface by which a browser may make the visibility state of a particular page available to the page itself. The browser may track the visibility state of the page as it changes and store the state in a variable associated with the page. Code executing within the page may query this variable to determine the visibility state and take appropriate action. The browser may provide an application programming interface (API) to allow the page to request the visibility state.Type: ApplicationFiled: December 1, 2011Publication date: July 9, 2015Applicant: GOOGLE INC.Inventors: Shishir Kumar Agrawal, John Alexander Komoroske
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Patent number: 9006841Abstract: A dual port SRAM has two data storage nodes, a true data and complementary data. A first pull down transistor has an active area that forms the drain region of the first transistor and the true data storage node that is physically isolated from all other transistor active areas of the memory cell. A second pull down transistor has an active area that forms the drain region of a second transistor that is the complementary data node that is physically isolated from all other transistor active areas of the memory cell.Type: GrantFiled: August 22, 2012Date of Patent: April 14, 2015Assignee: STMicroelectronics International N.V.Inventors: Shishir Kumar, Dibya Dipti, Pierre Malinge
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Publication number: 20150055400Abstract: Delays are introduced in self-timed memories by introducing a capacitance on the path of a signal to be delayed. The capacitances are realized by using idle-lying metal layers in the circuitry. The signal to be delayed is connected to the idle-lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal, which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since idle-lying metal capacitances are utilized, the circuitry can be implemented using a minimum amount of additional hardware. Also, the delay provided by the circuitry is a function of memory cell SPICE characteristics and core parasitic capacitances.Type: ApplicationFiled: November 4, 2014Publication date: February 26, 2015Inventors: NISHU KOHLI, MUDIT BHARGAVA, SHISHIR KUMAR
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Patent number: 8963053Abstract: Delays are introduced in self-timed memories by introducing a capacitance on the path of a signal to be delayed. The capacitances are realized by using idle-lying metal layers in the circuitry. The signal to be delayed is connected to the idle-lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal, which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since idle-lying metal capacitances are utilized, the circuitry can be implemented using a minimum amount of additional hardware. Also, the delay provided by the circuitry is a function of memory cell SPICE characteristics and core parasitic capacitances.Type: GrantFiled: March 5, 2012Date of Patent: February 24, 2015Assignee: STMicroelectronics PVT. Ltd.Inventors: Nishu Kohli, Mudit Bhargava, Shishir Kumar
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Publication number: 20150029795Abstract: A write is performed to a first cell of a memory at a first row and column during a first memory access cycle. A memory access operation is made to a second cell at a second row and column during an immediately following second memory access cycle. If the memory access is a read from the second cell and the second row is the same as the first row, or if the memory access is a write to the second cell and the second row is the same as the first row and the second column is different than the first column, then a simultaneous operation is performed during the second memory access cycle. The simultaneous operation is an access of the second cell (for read or write) and a re-write of data from the first memory access cycle write operation back to the first cell.Type: ApplicationFiled: July 24, 2013Publication date: January 29, 2015Applicant: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Nishu Kohli, Shishir Kumar
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Publication number: 20140204656Abstract: A memory cell includes a latch having a true data node and a complement data node, a true bitline, a complement bitline, a first access transistor coupled between the true bitline and the true data node, and a second access transistor coupled between the complement bitline and the complement data node. A wordline driver circuit includes a true wordline coupled to control the first access transistor and a complement wordline coupled to control the second access transistor. The wordline driver generates control signals on the true and complement wordlines to access the memory cell by: actuating the first access transistor while the second access transistor is not actuated and then actuating the second access transistor while the first access transistor is not actuated. The bitlines and wordlines are supplied from different sets of power supply voltages, with the bitline high supply voltage being less than the wordline high supply voltage.Type: ApplicationFiled: January 22, 2013Publication date: July 24, 2014Applicant: STMICROELECTRONICS INTERNATIONAL N.V.Inventor: Shishir Kumar
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Publication number: 20130170275Abstract: A dual port SRAM has two data storage nodes, a true data and complementary data. A first pull down transistor has an active are that forms the drain region of the first transistor and the true data storage node that is physically isolated from all other transistor active areas of the memory cell. A second pull down transistor has an active area that form the drain region of a second transistor that is the complementary data node that is physically isolated from all other transistor active areas of the memory cell.Type: ApplicationFiled: August 22, 2012Publication date: July 4, 2013Applicant: STMicroelectronics Pvt. Ltd.Inventors: Shishir Kumar, Dibya Dipti, Pierre Malinge
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Publication number: 20120170393Abstract: Delays are introduced in self-timed memories by introducing a capacitance on the path of a signal to be delayed. The capacitances are realized by using idle-lying metal layers in the circuitry. The signal to be delayed is connected to the idle-lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal, which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since idle-lying metal capacitances are utilized, the circuitry can be implemented using a minimum amount of additional hardware. Also, the delay provided by the circuitry is a function of memory cell SPICE characteristics and core parasitic capacitances.Type: ApplicationFiled: March 5, 2012Publication date: July 5, 2012Applicant: STMICROELECTRONICS PVT.LTD.Inventors: Nishu Kohli, Mudit Bhargava, Shishir Kumar
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Patent number: 8138455Abstract: A novel method for introducing delays in self timed memories is disclosed. In the proposed method, delays are introduced by introducing a capacitance on the path of signal to be delayed. The capacitances are realized by using idle lying metal layers in the circuit. The signal to be delayed is connected to these idle lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since, in the proposed method, idle-lying metal capacitances are utilized, the circuit can be implemented using minimum amount of additional hardware. Also delay provided by the proposed circuitry is a function of memory cell spice characteristics and core parasitic capacitances.Type: GrantFiled: December 28, 2006Date of Patent: March 20, 2012Assignee: STMicroelectronics Pvt. Ltd.Inventors: Nishu Kohli, Mudit Bhargava, Shishir Kumar
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Patent number: 7545180Abstract: A sense amplifier circuit provides for high speed sensing with a high speed read operation, with a low capacitance and a low resolution time. The sense amplifier circuit includes a latch circuit having a first inverter circuit and a second inverter circuit cross coupled with each other. The amplifier circuit includes a first discharge device and a second discharge device operatively coupled to the first inverter circuit and the second inverter circuit respectively. The amplifier circuit further includes a first PMOS transistor operatively coupled between the first discharge device and a bit line, and a second PMOS transistor operatively coupled between the second discharge device and a complementary bit line. The amplifier circuit further includes a first NMOS transistor operatively coupled between the first discharge device and a ground voltage, a second NMOS transistor operatively coupled between the second discharge device and the ground voltage.Type: GrantFiled: September 26, 2007Date of Patent: June 9, 2009Assignee: STMicroelectronics PVT. Ltd.Inventors: Ankur Goel, Mudit Bhargava, Shishir Kumar
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Publication number: 20080143390Abstract: A sense amplifier circuit provides for high speed sensing with a high speed read operation, with a low capacitance and a low resolution time. The sense amplifier circuit includes a latch circuit having a first inverter circuit and a second inverter circuit cross coupled with each other. The amplifier circuit includes a first discharge device and a second discharge device operatively coupled to the first inverter circuit and the second inverter circuit respectively. The amplifier circuit further includes a first PMOS transistor operatively coupled between the first discharge device and a bit line, and a second PMOS transistor operatively coupled between the second discharge device and a complementary bit line. The amplifier circuit further includes a first NMOS transistor operatively coupled between the first discharge device and a ground voltage, a second NMOS transistor operatively coupled between the second discharge device and the ground voltage.Type: ApplicationFiled: September 26, 2007Publication date: June 19, 2008Applicant: STMicroelectronics PVT. LTD.Inventors: Ankur Goel, Mudit Bhargava, Shishir Kumar
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Publication number: 20070201287Abstract: A novel method for introducing delays in self timed memories is disclosed. In the proposed method, delays are introduced by introducing a capacitance on the path of signal to be delayed. The capacitances are realized by using idle lying metal layers in the circuit. The signal to be delayed is connected to these idle lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since, in the proposed method, idle-lying metal capacitances are utilized. the circuit can be implemented using minimum amount of additional hardware. Also delay provided by the proposed circuitry is a function of memory cell spice characteristics and core parasitic capacitances.Type: ApplicationFiled: December 28, 2006Publication date: August 30, 2007Applicant: STMicroelectronics Pvt. Ltd.Inventors: Nishu Kohli, Mudit Bhargava, Shishir Kumar