Abstract: A CDMA receiver is provided which is operable to receive a CDMA encoded signal and decode the information therein utilizing a selected code. The systems utilizes a plurality of multiply-accumulation blocks (40) which are operable to receive the signal and compare the received signal with a Walsh-Hadamard code. The comparison and the accumulation is made only in the middle of a chip clock with the edges thereof blanked. This information in the middle of the chip clock is accumulated in an accumulator, the MAC (40), for a symbol period. This is then compared with a look up table and then a decision made as to the logic value thereof.

Abstract: A digital camera (10) that has an array (11) of CMOS sensor elements (11a). The array (11) is read in a manner that performs spatial-to-frequency transforms for image compression on the analog output signals of the sensor elements. More specifically, wordlines (12) and bitlines (13) are pulsewidth modulated so that the coincidence of their “on” times corresponds to a desired coefficient of the basis function of the transform (FIGS. 3 and 4). Additional comparator circuitry (15), quantizers (16), and encoding circuitry (19) can be part of the same integrated circuit as the array (11).

Abstract: An absolute time scale clock includes a radioactive isotope and a computer. The computer includes a processor that determines an indication of the current absolute time and a memory that stores a decay constant of the radioactive isotope, a reference time, and an amount of the isotope at the reference time. A energy supply that provides power to the computer. The absolute time scale clock further includes a detector positioned to respond to emissions from the radioactive isotope. The detector generates an indication of the number of emissions over a time interval that varies with the decay rate of the isotope. The processor is responsive to the indication from the detector, the decay constant, the reference time, and the reference amount to determine the indication of current absolute time.

Abstract: This invention corrects of white spot noise in an imager. If the brightness value of a pixel is greater than the maximum brightness value of eight surrounding pixels, then the compensated output is this maximum brightness value. If the brightness value of the pixel is less than the maximum brightness value, then no compensation is applied. Alternatively the brightness value of the pixel may be compared with the maximum brightness value plus a threshold value. The invention stores correction values for a few pixels. If a particular pixel has a stored correction value, then this is subtracted from the brightness value of the particular pixel and the maximum brightness correction is applied to this difference. The stored correction value is replaced with the difference between the brightness value of the particular pixel and the maximum brightness value if this difference is greater than the stored correction value.

Abstract: An absolute time scale clock includes a radioactive isotope and a computer. The computer includes a processor that determines an indication of the current absolute time and a memory that stores a decay constant of the radioactive isotope, a reference time, and an amount of the isotope at the reference time. A energy supply that provides power to the computer. The absolute time scale clock further includes a detector positioned to respond to emissions from the radioactive isotope. The detector generates an indication of the number of emissions over a time interval that varies with the decay rate of the isotope. The processor is responsive to the indication from the detector, the decay constant, the reference time, and the reference amount to determine the indication of current absolute time.

Abstract: A digital camera (10) that has an array (11) of CMOS sensor elements (11a). The array (11) is read in a manner that performs spatial-to-frequency transforms for image compression on the analog output signals of the sensor elements. More specifically, wordlines (12) and bitlines (13) are pulsewidth modulated so that the coincidence of their “on” times corresponds to a desired coefficient of the basis function of the transform (FIGS. 3 and 4). Additional comparator circuitry (15), quantizers (16), and encoding circuitry (19) can be part of the same integrated circuit as the array (11).

Abstract: A digital camera (10) that has an array (11) of CMOS sensor elements (11a). The array (11) is read in a manner that performs spatial-to-frequency transforms for image compression on the analog output signals of the sensor elements. More specifically, wordlines (12) and bitlines (13) are pulsewidth modulated so that the coincidence of their “on” times corresponds to a desired coefficient of the basis function of the transform (FIGS. 3 and 4). Additional comparator circuitry (15), quantizers (16), and encoding circuitry (19) can be part of the same integrated circuit as the array (11).

Abstract: A cable modem (20) having a blind equalizer (40) in its equalization function (28) is disclosed. The blind equalizer (40) includes an adaptive equalizer (44) and an approximating update function (42) that provides updated equalization coefficients to the adaptive equalizer (44) using the Constant Modulus Algorithm, wherein the error in the adaptive equalizer output is estimated. The estimates are based upon a determination of the maximum and minimum of the real and i components of symbols output by the adaptive equalizer (44). Efficiency in the computations required for updating the equalizer coefficients is obtained, without sacrificing convergence.

Abstract: A data converter (20) comprising an input (I0′-I3′) for receiving a digital word and an output (VOUT2) for providing an analog voltage level in response to the digital word. The data converter further comprises a plurality of bit lines (BL0′-BL3′) formed with an alignment in a first dimension and a plurality of word lines (WL0′-WL4′) formed with an alignment in a second dimension different than the first dimension. Further, the data converter comprises a string (12′) comprising a plurality of series connected resistive elements (R0′-R14′). The string comprises a plurality of voltage taps (T0′-T15′), and at least a majority of the plurality of series connected resistive elements are formed with an alignment in the first dimension. The data converter also comprises a plurality of switching transistors (ST0′-ST15′) coupled between the plurality of voltage taps and the output.

Abstract: A data converter (20) comprising an input (I0′-I3′) for receiving a digital word and an output (VOUT2) for providing an analog voltage level in response to the digital word. The data converter further comprises a plurality of bit lines (BL0′-BL3′) formed with an alignment in a first dimension and a plurality of word lines (WL0′-WL4′) formed with an alignment in a second dimension different than the first dimension. Further, the data converter comprises a string (12′) comprising a plurality of series connected resistive elements (R0′-R14′). The string comprises a plurality of voltage taps (T0′-T15′), and at least a majority of the plurality of series connected resistive elements are formed with an alignment in the first dimension. The data converter also comprises a plurality of switching transistors (ST0′-ST15′) coupled between the plurality of voltage taps and the output.

Abstract: A conducting path with a path meander provides a precision voltage-dividing circuit. At each location wherein a voltage level is to be established, the conducting path has an expanded region called a junction region. The centers of all junction regions are equidistant from the centers of neighboring junction regions. Junction regions are positioned at predetermined intervals along the straight portions of the conducting path and at each corner of the path meander. Each junction region has a metal patch extending therefrom. The metal patches are coupled to conducting plugs that, in turn, can be coupled to switching elements of a digital-to-analog converter unit. The junction regions can be altered to increase the precision of the voltage-dividing circuit. Because the junction regions are equidistant from the neighboring junction regions, a cell that includes the switching elements can have a square geometry.

Abstract: A data converter (20). The converter comprises an input (I0-I3) for receiving a digital word. The converter further comprises a string (22) of series connected resistive elements. The string comprises an integer number T of voltage taps (T0′-T8′). The converter further comprises an output (VOUT2) for providing an integer number P of different analog voltage levels in response to the digital word. The integer number P is greater than the integer number T.

Abstract: An analog-to-digital converter (“ADC”, 40) comprising an input (VIN2) for receiving an input analog voltage. The ADC further comprises a digital-to-analog circuit, comprising a meandering string (12′) of series connected resistive elements (R0′-R14′) having a plurality of voltage taps (T0′-T15′), as well as a number of bit lines (BL0′-BL3′) and a number of word lines (WL0′-WL3′). For a given input analog voltage, the given input analog voltage is closest to a voltage at a selected one of the plurality of taps. In addition, the selected one of the plurality of taps is associated with one of the number of bit lines and one of the number of word lines. Additionally, the ADC further comprises a flash circuit (44, 46, 48, 50, 42, CAT0′-CAT3′) coupled to receive the input analog voltage from the input and in response to identify either the one of the number of bit lines or the one of the number of word lines.

Abstract: A data converter (20). The data converter comprises an input (I0′-I3′) for receiving a digital word and an output (VOUT2) for providing an analog voltage level in response to the digital word. The data converter further comprises at least one string (12′) of series connected resistive elements (R0′-R14′). The at least one string comprises a plurality of voltage taps (T0′-T14′)and is operable to receive a string bias of X volts (VREF2). Lastly, the data converter comprises a plurality of switching transistors (ST0n-ST15n; ST0p-ST15p) coupled between the plurality of voltage taps and the output. Specifically, responsive to at least a portion of the digital word, selected ones of the switching transistors are operable to receive a gate bias to enable the corresponding switching transistor to provide a conductive path from a corresponding one of the voltage taps toward the output. In addition, the difference between X volts and the gate bias is less than approximately 2.

Abstract: Two thermometer coded words having a most significant byte (MSB) and a least significant byte (LSB) are subtracted, and a check detects a borrowing condition. A first borrowing condition is detected if word B MSB is greater than word A MSB (12), and word A LSB is greater than word B LSB (14). In such a case a borrow (16) must take place on word B MSB. A second borrowing condition is detected when the word A MSB is greater than the word B MSB (18) and the word B LSB is greater than the word A LSB (20). In this instance, a borrow (22) should take place on word A MSB through a shift right function. After borrowing, a subtraction (24) takes place by exclusive-or'ing word A and B MSBs. The result is reconstructed (26) through a shift right process into proper thermometer code format. If a borrowing condition exists, an appropriate LSB is translated (28, 30) before an LSB subtraction process (32) takes the resulting word A and word B LSBs and exclusively-or's them together.

Abstract: A digital to analog converter (“DAC”) (20). The DAC includes an input (23) for receiving a plurality of successive digital words (D3−D0), and circuitry (28, 30) for storing the plurality of successive digital words. The DAC also includes a string (12′) of series connected resistive elements, wherein the string comprises a plurality of voltage taps (T0′-T15′). The DAC further includes an output (OUTA) for providing an analog output voltage corresponding to a selected one of the plurality of successive digital words. The DAC further includes comparison circuitry (32) for comparing the selected one and an earlier received one of the plurality of successive digital words. Finally, the DAC includes circuitry (34, 24, 26) for generating the analog output voltage in response to the comparison circuitry.

Abstract: A data converter (20) comprising an input (I0′-I2′) for receiving an input signal and an output (VOUT′) for providing an output signal formed in response to the input signal. The converter also includes a string of series-connected resistive elements (12′) having in total a string resistance (DENOM) and providing a plurality of voltage taps (T0′-T7′), wherein at least one of the voltage taps is accessible in response to the input signal and for forming the output signal. The converter further includes a calibration circuit (22). The calibration circuit includes a plurality of trimming transistors (TT0-TT6) connected in parallel to selected ones of the plurality of voltage taps. Each of the trimming transistors has an adjustable resistance.

Abstract: An image encoding/decoding system (10) includes an encoder section (12) and a decoder section (14). The encoder section (12) includes an image detector (15), a transform processor (16), a quantizer (18), a zig-zag process memory (20), and a run/variable length encoder (22). The decoder section includes a variable/run length decoder (24), a dequantizer (26), a zig-zag deprocess memory (28), and an inverse transform processor (30). The inverse transform processor (30) within the decoder section (14) uses basis functions (58) based on a discrete articulated trapezoid transform for ease of realizability in decoding image data. The discrete articulated trapezoid transform may also be used by the transform processor (16) within the encoder section (12) for the encoding of detected images.

Abstract: A data converter (20) comprising an input (I.sub.0 '-I.sub.3 ') for receiving a digital word and an output (V.sub.OUT2) for providing an analog voltage level in response to the digital word. The data converter further comprises a plurality of bit lines (BL0'-BL3') formed with an alignment in a first dimension and a plurality of word lines formed (WL0'-WL3') with an alignment in a second dimension different than the first dimension. Still further, the data converter comprises a string (12') comprising a plurality of series connected resistive elements (R10-R24) and a plurality of voltage taps (T10-T25), where at least a majority of the plurality of series connected resistive elements are formed with an alignment in the second dimension. Lastly, the data converter comprises a plurality of switching transistors (ST10-ST25) coupled between the plurality of voltage taps and the output.

Abstract: A Hamming distance calculation device (10) includes a bit comparator (12) for determining nonmatching bit positions between two digital words. A current signal is generated for each nonmatching bit position by a nonmatching current generator (14). The current signals created are combined to produce a summed current signal that drives a first reference current comparator (18), a second reference current comparator (20), and an nth reference current comparator (22). The first reference current comparator (18) compares the summed current signal with a reference current signal to produce an output and a select signal that determines a reference current signal used in the second reference current comparator (20). The second reference current comparator (20) compares the summed current signal with a reference current signal as selected by the first reference current comparator (18) and produces an output in response thereof.