Abstract: A gate array base cell which can easily be configured as high conductivity transistor device or a low conductivity transistor device comprises a moat region of first conductivity type, typically heavily doped n-type silicon or heavily doped p-type silicon, for example. A channel region of a different conductivity type separates the moat region into at least three portions. An insulating layer, such as silicon dioxide, for example, and a gate are formed above the channel region. The gate may be formed of polysilicon, for example. Modifications, variations, circuit configurations and an illustrative fabrication method are also disclosed.

Abstract: A multiply accumulate unit processes a signal according to a sum-of-products function based upon a plurality of multibit sampled values and a corresponding plurality of multibit constants. A multiply-add block receives the sampled values and the constants. A portion of each constant is selected. A plurality of multipliers multiple sampled values and selected portions of the corresponding constants. The products are added and shifted corresponding to the significance of the selected portion of the constants. These are added to generate a sum of sequential outputs of the multiply-add block. The multiply accumulate unit repeats operation employing the same sample values but portions of said corresponding constants having sequentially less significant bits. This sequence repeats until the sum of all prior sum-of-products functions has a desired level of accuracy.

Abstract: An active load (12) is provided for an N channel logic network (10). The active load (12) includes a P channel device (28) coupled to the output node (14) of the N channel network (10). A clock circuit (16) of the active load (12) determines whether the N channel network (10) is in a steady state or a switching mode. If the N channel network (10) is in a switching mode, an intermediate voltage level, V.sub.bias, is applied at the gate of the P channel device (28) to facilitate fast switching at the output node (14) with low quiescent power consumption and without compromising compact semiconductor layout.

Abstract: The gate array (10) has a first doped region (14) in a semiconductor substrate (12) and a plurality of contacts (20-20"', 21-21") arranged in rows and columns to the first doped region (14) organized with contacts of each row offset in a column (25) that is spaced with respect to a columns (28) of adjacent rows at which a contact exists. A plurality of gate conductors (35-42) are arranged to circumnavigate successive contacts (20,21) of adjacent rows on opposite sides in a serpentine patterns, preferably that follow partially circular paths. The contacts (20,21) are substantially circular in cross section, and may be provided with cap (32) on each that may also have a substantially circular cross section. The contacts (20-21) are spaced with a predetermined pitch and the gate conductors (35-42) have a width that defines transistor channels between adjacent contacts. The width of the conductors (35-42) allows the conductors to pass in proximity to the contacts (20-21) with a predetermined spacing.

Abstract: A flip-flop circuit which includes a master section (1) having a pair of back to back connected inverters (5, 7) to form a latch circuit with their ground terminals connected together. The clock signal is coupled to the ground terminal of the inverters (5,7) to provide a negative gate to source voltage rather than an essentially zero gate to source voltage as used in prior art inverters to insure full turn off of the inverter transistors (40, 45) during their off periods and conserving power thereby. When the first phase of the clock signal goes high, the signal on the data line is fed to one side of the latch and the other side of the latch is coupled to ground or reference voltage. When the first phase of the clock then goes low, the signal from the data line is latched into the latch of the master section (1) and the other side of that latch is decoupled from ground.

Abstract: Memory chips with data memory (202), embedded logic (206) and broadcast memory (204) for two modes of operation are disclosed. A first mode of operation is the usual memory mode expected of a data RAM. The second mode of operation allows localized computation and/or processing of the data in data memory (202) by the embedded logic (206) with minimal handshaking with a remote CPU. In a functioning system, the memory chips are organized in a hierarchical manner and include address-associative memory systems.

Abstract: A device is disclosed which combines the advantages of CMOS and bipolar using an existing parasitic bipolar device. As such high on-chip density is attainable with the device along with high speed capability while maintaining low power advantages.

Abstract: For subtracting two thermometer coded words each having a most significant byte (MSB) and a least significant byte (LSB), a check is made to see if a borrowing condition exists. A first borrowing condition exists if word B MSB is greater than word A MSB (12) and word A LSB is greater than word B LSB (14). In such a case a borrow (16) must take place on word B MSB. A second borrowing condition exists when word A MSB is greater than word B MSB (18) and word B LSB is greater than word A LSB (20). In this instance a borrow (22) must take place on word A MSB through a shift right function. After borrowing occurs, a subtraction process (24) takes place by exclusive-or'ing word A and B MSBs. The result is reconstructed (26) through a shift right process into proper thermometer code format. If a borrowing condition exists, an appropriate LSB is translated (28, 30) before an LSB subtraction process (32) takes the resulting word A and word B LSBs and exclusively-or's them together.

Abstract: A signal transmission system (10) is provided that comprises a transmitter circuit (12) which transmits a signal through a transmission line (16) to a receiver circuit (14) using the current mode of signal transmission. A steady state current is supplied by a steady state current source (22). An active state current is provided by an active current source (20). A boost circuit (18) is provided to reduce delay associated with the transmission line (16) by increasing charge to the transmission line and providing additional discharge path from the transmission line during transitions of the signal propagating along transmission line (16).

Abstract: A semiconductor 110 device includes an array of like base cells wherein each base cell includes at least one source 132 and at least one drain 130 region formed in a semiconductor substrate. At least one gate 126 is formed over and insulated from a channel region 118 which separates the source 132 and drain 130 regions. An insulating layer 190 overlies the structure. A plurality of contacts are formed in the insulating layer in a plurality of substantially parallel; evenly spaced grid lines G1-G5. In addition, at least one additional contact 150 formed between two adjacent ones G2 and G3 of the substantially parallel grid lines is formed. A plurality of interconnect lines 142 and 144 are formed over the insulating layer such that each contact is connected to at least one of the interconnect lines. Modifications, variations, circuit configurations and an illustrative fabrication method are also disclosed.

Abstract: A gate array base cell which can easily be configured as high conductivity transistor device or a low conductivity transistor device comprises a moat region of first conductivity type, typically heavily doped n-type silicon or heavily doped p-type silicon, for example. A channel region of a different conductivity type separates the moat region into at least three portions. An insulating layer, such as silicon dioxide, for example, and a gate are formed above the channel region. The gate may be formed of polysilicon, for example. Modifications, variations, circuit configurations and an illustrative fabrication method are also disclosed.

Abstract: A signal transmission system (10) is provided that comprises a transmitter circuit (12) which transmits a signal through a transmission line (16) to a receiver circuit (14) using the current mode of signal transmission. A steady state current is supplied by a steady state current source (22). An active state current is provided by an active current source (20). A boost circuit (18) is provided to reduce delay associated with the transmission line (16) by increasing charge to the transmission line and providing additional discharge path from the transmission line during transitions of the signal propagating along transmission line (16).

Abstract: An active memory 14 is provided which includes a data memory 20 including rows and columns of storage locations for holding data. A broadcast memory 22 is provided which includes rows and columns of storage locations for holding control instructions. Search circuitry 26, 52 is provided which is operable to receive at least one word of data from data memory 20 and test the word against a preselected search test condition. Control circuitry 24 is operable in response to control instructions received from the broadcast memory 22 to control the transfer of the word of data from the data memory 20 to the search circuitry 26, 52 and the test of the word by the search circuitry 26, 52.

Abstract: A base cell for a CMOS gate array is provided with a plurality of N-channel transistors 10, 12, 14 with all such N-channel transistors coupled in series. A plurality of P-channel transistors 16, 18 coupled in series. These transistors are interconnected at the transistor level to form a partially prewired circuit. Specifically, the gates of two of the N-channel transistors 12, 14 are connected by polysilicon lead 28 to the gate of transistor 16. This configuration forms a circuit primitive which is well adapted for use as a base cell in a programmable array device.

Abstract: An adder-based base cell (10) is provided for field programmable gate arrays. The base cell (10) includes a first inverter (13) operable to receive a first input signal (A). A first NAND gate (12) is coupled to the first inverter (13) and is operable to receive a second input signal (B). A first 2:1 multiplexer (14) is coupled to the first NAND gate (12) and is operable to receive a third input signal (C). The output of the first 2:1 multiplexer (14) represents a first function (F1). A second inverter (17) is operable to receive a fourth input signal (D). A second NAND gate (16) is coupled to the second inverter (17) and is operable to receive a fifth input signal (E). An XOR gate (18) is coupled to the second NAND gate (16), is operable to receive a sixth input signal (F), and is coupled to the first 2:1 multiplexer (14). The output of the XOR gate represents a partial sum function (PS.sub.-- 1).

Abstract: A gate array base cell which can easily be configured as high conductivity transistor device or a low conductivity transistor device comprises a moat region of first conductivity type, typically heavily doped n-type silicon or heavily doped p-type silicon, for example. A channel region of a different conductivity type separates the moat region into at least three portions. An insulating layer, such as silicon dioxide, for example, and a gate are formed above the channel region. The gate may be formed of polysilicon, for example. Modifications, variations, circuit configurations and an illustrative fabrication method are also disclosed.

Abstract: A flip-flop designed for use in gate arrays following LSSD design rules. The flip-flop has a data input D and a scan data input SD which are gated by control signals fmc, fmc' to the flip-flop input terminal 18. The flip-flop input 18 is gated into a master flip-flop consisting of two inverters 30, 32 coupled back-to-back by a gate signal DMC which is valid when the desired input signal is gated to the flip-flop input 18. The master flip-flop is coupled to a slave flip-flop which is gated by a different control signal. The slave flip-flop consists of two inverters 44, 46 coupled back-to-back. Inverters 48, 50 coupled to the slave flip-flop provide a buffered output therefrom.

Abstract: A base cell for a CMOS gate array is provided with a first plurality of N-channel transistors 12, 14, 16 with two such N-channel transistors coupled in series. A first plurality of P-channel transistors 50, 52, 54 with two such P-channel transistors coupled in series. These transistors are interconnected at the transistor level to form a partially prewired circuit. Additional pairs of series connected N-channel transistors (18, 20), (22, 24) and pairs of series connected P-channel transistors (56, 58), (60, 62) are also provided and are interconnected at the transistor level to form additional partially prewired circuits. By adding additional levels of wiring 100, 102, the base cell can be finally wired to form a plurality of different logic circuits.

Abstract: An arithmetic and logic unit implemented in a memory array.

Abstract: A base cell for a CMOS gate array is provided with a plurality of N-channel transistors 10 and a plurality of P-channel transistors 12. These transistors are interconnected at the transistor level to form a partially prewired circuit. Additional N-channel (14) and P-channel (70, 72) transistors are included in the base cell at least some of which are larger in size than those in the plurality of N-channel transistors 10 or the plurality of P-channel transistors 12. These larger size transistors are used as output drivers to send the logical output signal of the cell to another cell.