Patents by Inventor Shogo Okita

Shogo Okita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11551974
    Abstract: A manufacturing process of an element chip comprises a preparing step for preparing a substrate having first and second sides opposed to each other, the substrate containing a semiconductor layer, a wiring layer and a resin layer formed on the first side, and the substrate including a plurality of dicing regions and element regions defined by the dicing regions. Also, the manufacturing process comprises a laser grooving step for irradiating a laser beam onto the dicing regions to form grooves so as to expose the semiconductor layer along the dicing regions. Further, the manufacturing process comprises a dicing step for plasma-etching the semiconductor layer along the dicing regions through the second side to divide the substrate into a plurality of the element chips. The laser grooving step includes a melting step for melting a surface of the semiconductor layer exposed along the dicing regions.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: January 10, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hidefumi Saeki, Atsushi Harikai, Shogo Okita
  • Publication number: 20220402072
    Abstract: An element chip manufacturing method includes a step of preparing a substrate including a semiconductor layer and a wiring layer formed on the semiconductor layer, the substrate having element regions and a dicing region defining the element regions, a laser grooving step of irradiating a laser beam to the wiring layer at the dicing region, to form an aperture exposing the semiconductor layer, and a step of etching the semiconductor layer exposed from the aperture, with plasma, to divide the substrate into a plurality of element chips. The laser grooving step includes a step of irradiating a first laser beam having a first pulse width, to remove the wiring layer in an edge portion of the dicing region, and a step of irradiating a second laser beam having a second pulse width which is longer than the first pulse width, to remove the wiring layer inside from the edge portion.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 22, 2022
    Inventors: Hidefumi SAEKI, Hidehiko KARASAKI, Shogo OKITA, Atsushi HARIKAI, Akihiro ITOU
  • Publication number: 20220406660
    Abstract: An element chip manufacturing method includes a step of preparing a substrate including a semiconductor layer and a wiring layer formed on the semiconductor layer and having a plurality of element regions and a dicing region defining the element regions, a laser grooving step of irradiating a laser beam to the wiring layer at the dicing region, to form an aperture exposing the semiconductor layer, and an individualization step of etching the semiconductor layer exposed from the aperture, with plasma, to divide the substrate into a plurality of element chips. The laser grooving step including a step of irradiating a first laser beam, to form a first groove exposing the semiconductor layer in the dicing region, and a step of irradiating a second laser beam, with a beam center positioned outside a side wall of the first groove, to widen the first groove into the aperture.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 22, 2022
    Inventors: Shogo OKITA, Hidehiko KARASAKI, Hidefumi SAEKI, Atsushi HARIKAI
  • Publication number: 20220384177
    Abstract: A method including: a step of preparing a substrate that includes a first layer having a first principal surface provided with a dicing region, and a mark, and a second principal surface, and includes a semiconductor layer; a step of covering a first region corresponding to the mark on the second principal surface, with a resist film; a step of forming a metal film on the second principal surface; a step of removing the resist film, to expose the semiconductor layer corresponding to the first region; a step of imaging the substrate, with a camera, to detect a position of the mark through the semiconductor layer, and calculating a second region corresponding to the dicing region on a surface of the metal film; and a step of irradiating a laser beam to the second region, to remove the metal film and expose the semiconductor layer corresponding to the second region.
    Type: Application
    Filed: May 16, 2022
    Publication date: December 1, 2022
    Inventors: Hidehiko KARASAKI, Shogo OKITA
  • Publication number: 20220367273
    Abstract: A method including: a step of preparing a substrate that includes a first layer having a dicing region and a mark, and including a semiconductor layer, and a second layer including a metal film; a step of removing the metal film, to expose the semiconductor layer corresponding to a first region that corresponds to the mark; a step of smoothing a surface of the exposed semiconductor layer; a step of imaging the substrate, with a camera sensing predetermined electromagnetic waves, to detect a position of the mark through the semiconductor layer, and calculating a second region corresponding to the dicing region; and a step of removing the metal film, to expose the semiconductor layer corresponding to the second region. In the smoothing step, the surface of the semiconductor layer is smoothed so as to have a surface roughness of 1/4 or less of a wavelength of the predetermined electromagnetic waves.
    Type: Application
    Filed: May 2, 2022
    Publication date: November 17, 2022
    Inventors: Hidehiko KARASAKI, Shogo OKITA
  • Publication number: 20220262603
    Abstract: A dry etching apparatus plasma processes a wafer held by a carrier having a frame and an holding sheet. The carrier is placed on an electrode unit of a stage provided in a chamber. The electrode unit is cooled by a cooling section configured to cool the electrode unit. An upper face of the electrode unit is at least as large as the back side of the carrier. The holding sheet and the frame are cooled effectively by the heat transfer to the stage.
    Type: Application
    Filed: May 5, 2022
    Publication date: August 18, 2022
    Inventor: Shogo OKITA
  • Patent number: 11398372
    Abstract: A plasma processing apparatus that performs plasma processing to a substrate held on a transport carrier including a frame and a holding sheet that covers an opening of the frame includes: a transport mechanism that transports the transport carrier; a position measuring section that measures a position of the substrate to the frame; a plasma processing section that includes a plasma processing stage on which the transport carrier is loaded and a cover that covers the frame and a part of the holding sheet loaded on the plasma processing stage, and has a window section for exposing a part of the substrate; and a control section that controls the transport mechanism such that the transport carrier is loaded on the plasma processing stage to satisfy a positional relationship between the window section and the substrate based on the position information of the substrate to the frame.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: July 26, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Hiromi Asakura, Syouzou Watanabe, Noriyuki Matsubara, Mitsuru Hiroshima, Toshihiro Wada
  • Publication number: 20220199411
    Abstract: Disclosed is a method for producing element chips. The method includes: a preparing step of preparing a substrate 10 that is held on a holding sheet 22 that is supported by a frame 21, the substrate including element regions and dicing regions; a protective film forming step of forming a protective film 15 so as to cover the frame 21, the holding sheet 22, and the substrate 10; a patterning step of removing a part of the protective film 15 so as to expose the dicing regions of the substrate 10; a plasma dicing step including a process that uses a plasma that contains fluorine, the plasma dicing step being a step of individualizing the substrate 10 into a plurality of element chips; and a fluorine removing step of removing, together with the protective film 15, fluorine attached to the protective film 15 in the plasma dicing step.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 23, 2022
    Inventors: Toshiyuki TAKASAKI, Ryota FURUKAWA, Atsushi HARIKAI, Shogo OKITA
  • Patent number: 11361944
    Abstract: A plasma processing method, including: a trenched substrate preparation process of preparing a trenched substrate having trenches having a bottom exposing an oxide film; and an oxide film removal process of exposing the trenched substrate to a plasma, to remove the oxide film. The oxide film removal process includes a plurality of cycles, each cycle including: an oxide film etching step of etching the oxide film; and a cleaning step of removing an attached matter on inner walls of the trenches, after the oxide film etching step.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: June 14, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita
  • Publication number: 20220181188
    Abstract: A plasma processing method including: a process of placing a work piece on a stage provided in a chamber, the work piece including a substrate and a holding member having an adhesive layer on a surface and holding the substrate via the adhesive layer, and having an exposed portion where the adhesive layer is exposed outside the substrate; and a plasma etching process of etching the substrate with a plasma generated in the chamber, with the exposed portion exposed to the plasma. In response to occurrence of an interruption in the plasma etching process, a cleaning process of exposing a surface of the substrate to a plasma containing an oxidizing gas is performed, and then the plasma etching process is resumed.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 9, 2022
    Inventors: Atsushi Harikai, Shogo Okita, Akihiro Itou
  • Publication number: 20220181209
    Abstract: The element chip manufacturing method includes: a preparing process of preparing a substrate 1 including a plurality of element regions EA and a dividing region DA, the substrate 1 having a first principal surface 1X and a second principal surface 1Y; a groove forming process of forming a groove 13 in the dividing region DA from the first principal surface 1X side; and a grinding process of grinding the substrate 1 from the second principal surface 1Y side, to divide the substrate 1 into a plurality of element chips 20. The groove 13 includes a first region 13a constituted by a side surface having a first surface roughness, and a second region 13b constituted by a side surface having a second surface roughness larger than the first surface roughness. In the grinding process, grinding of the substrate 1 is performed until reaching the first region 13a of the groove 13.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 9, 2022
    Inventors: Atsushi HARIKAI, Shogo OKITA, Akihiro ITOU, Toshiyuki TAKASAKI
  • Patent number: 11355323
    Abstract: A dry etching apparatus plasma processes a wafer held by a carrier having a frame and an holding sheet. The carrier is placed on an electrode unit of a stage provided in a chamber. The electrode unit is cooled by a cooling section configured to cool the electrode unit. An upper face of the electrode unit is at least as large as the back side of the carrier. The holding sheet and the frame are cooled effectively by the heat transfer to the stage.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: June 7, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Shogo Okita
  • Publication number: 20220165577
    Abstract: A plasma processing method including: exposing to a first plasma a substrate having a compound semiconductor layer and a mask partially covering a surface of the compound semiconductor layer, to form a protective film at least on the bottom of a groove formed in a region where the compound semiconductor layer is not covered with the mask; removing the protective film at the bottom by exposing the substrate to a second plasma, to expose the compound semiconductor layer; and removing the conductive semiconductor layer exposed at the bottom of the groove by exposing the substrate to a third plasma generated from a gas containing chlorine and/or bromine, while allowing a reaction product between the compound semiconductor layer and the third plasma to accumulate on an upper portion of the groove. The reaction product is removed by applying a high-frequency power to a stage on which the substrate is placed.
    Type: Application
    Filed: November 19, 2021
    Publication date: May 26, 2022
    Inventors: Toshiyuki TAKASAKI, Shogo OKITA, Akihiro ITOU, Atsushi HARIKAI
  • Patent number: 11335564
    Abstract: An element chip smoothing method including: an element chip preparation step of preparing at least one element chip including a first surface covered with a resin film, a second surface opposite the first surface, and a sidewall connecting the first surface to the second surface and having ruggedness; a sidewall cleaning step of exposing the element chip to a first plasma, to remove deposits adhering to the sidewall, with the resin film allowed to continue to exist; a sidewall oxidation step of exposing the element chip to a second plasma, after the sidewall cleaning step, to oxidize a surface of the sidewall, with the resin film allowed to continue to exist; and a sidewall etching step of exposing the element chip to a third plasma, after the sidewall oxidation step, to etch the sidewall, with the resin film allowed to continue to exist.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: May 17, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Akihiro Itou, Atsushi Harikai, Toshiyuki Takasaki, Shogo Okita
  • Patent number: 11289428
    Abstract: An element chip manufacturing method including: preparing a semiconductor substrate including a first layer having a first principal surface, and a second layer having a second principal surface, the first layer provided with element regions, a dicing region, and an alignment mark, wherein the first layer includes a semiconductor layer, and the second layer includes a metal layer adjacent to the semiconductor layer; irradiating a first laser beam absorbed in the metal film and passing through the semiconductor layer, from the second principal surface side to a first region corresponding to the mark; imaging the semiconductor substrate from the second principal surface side with a camera, and then calculating a second region corresponding to the dicing region on the second principal surface; irradiating a second laser beam to the second region from the second principal surface side; and dicing the semiconductor substrate into a plurality of element chips.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: March 29, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kiyoshi Arita, Shogo Okita, Hidehiko Karasaki
  • Patent number: 11219929
    Abstract: An element chip cleaning method including: an element chip preparation step of preparing at least one element chip having a first surface and a second surface opposite the first surface, the first surface covered with a resin film; a first cleaning step of bringing a first cleaning liquid into contact with the resin film, the first cleaning liquid including a solvent that dissolves at least part of a resin component contained in the resin film; and a second cleaning step of spraying a second cleaning liquid against the resin film from the first surface side of the element chip, after the first cleaning step.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: January 11, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Akihiro Itou, Atsushi Harikai, Toshiyuki Takasaki, Hidefumi Saeki, Shogo Okita
  • Publication number: 20210407855
    Abstract: A manufacturing process of an element chip comprises a preparing step for preparing a substrate having first and second sides opposed to each other, the substrate containing a semiconductor layer, a wiring layer and a resin layer formed on the first side, and the substrate including a plurality of dicing regions and element regions defined by the dicing regions. Also, the manufacturing process comprises a laser grooving step for irradiating a laser beam onto the dicing regions to form grooves so as to expose the semiconductor layer along the dicing regions. Further, the manufacturing process comprises a dicing step for plasma-etching the semiconductor layer along the dicing regions through the second side to divide the substrate into a plurality of the element chips. The laser grooving step includes a melting step for melting a surface of the semiconductor layer exposed along the dicing regions.
    Type: Application
    Filed: September 10, 2021
    Publication date: December 30, 2021
    Inventors: Hidefumi SAEKI, Atsushi HARIKAI, Shogo OKITA
  • Patent number: 11189480
    Abstract: An element chip manufacturing method including: a preparing step of preparing a substrate including a plurality of element regions and a dicing region defining the element regions, the substrate having a first surface and a second surface opposite the first surface; a laser scribing step of applying a laser beam to the dicing region from a side of the first surface, to form a groove corresponding to the dicing region and being shallower than a thickness of the substrate; a cleaning step of exposing the first surface of the substrate to a first plasma, to remove debris on the groove; and a dicing step of exposing the substrate at a bottom of the groove to a second plasma after the cleaning step, to dice the substrate into element chips including the element regions. The first plasma is generated from a process gas containing a carbon oxide gas.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: November 30, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Atsushi Harikai, Akihiro Itou
  • Patent number: 11145548
    Abstract: A manufacturing process of an element chip comprises a preparing step for preparing a substrate having first and second sides opposed to each other, the substrate containing a semiconductor layer, a wiring layer and a resin layer formed on the first side, and the substrate including a plurality of dicing regions and element regions defined by the dicing regions. Also, the manufacturing process comprises a laser grooving step for irradiating a laser beam onto the dicing regions to form grooves so as to expose the semiconductor layer along the dicing regions. Further, the manufacturing process comprises a dicing step for plasma-etching the semiconductor layer along the dicing regions through the second side to divide the substrate into a plurality of the element chips. The laser grooving step includes a melting step for melting a surface of the semiconductor layer exposed along the dicing regions.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: October 12, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hidefumi Saeki, Atsushi Harikai, Shogo Okita
  • Patent number: 11145494
    Abstract: In plasma processing, damage on a cover is prevented while thermal effect on an annular frame is suppressed. Plasma processing is applied to a substrate held by a carrier including an annular frame and a holding sheet. There are provided a chamber having a decompressible internal space, a plasma source for generating plasma in the chamber, a stage that is provided in the chamber and places the carrier thereon, and a cover that is placed above the stage to cover the holding sheet and the frame, and has a window penetrating through the thickness of the cover. The cover is made of a material having a high thermal conductivity, and a front face exposed to plasma, at least on the side of the window of the cover, is covered with a protect part made of a material having a low reactivity with plasma.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: October 12, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Mitsuhiro Okune