Patents by Inventor Shogo Okita

Shogo Okita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240162091
    Abstract: The disclosed element chip manufacturing method includes: a first step of imparting hydrophilicity to a first surface 11 of a substrate 1, the first surface 11 including element regions 11A and dicing regions 11B defining the element regions 11A; a second step of applying a raw material liquid containing a water-soluble resin onto the first surface 11, to form a water-soluble resin layer 20 on the first surface 11; a third step of applying a laser beam to the water-soluble resin layer 20 covering the dicing regions 11B, to form openings 20a that expose the dicing regions 11B, in the water-soluble resin layer 20; a fourth step of etching the dicing regions 11B exposed at the openings 20a, with plasma, to obtain element chips 30; and a fifth step of removing the water-soluble resin layer 20 by bringing the element chips 30 into contact with a water-containing cleaning liquid.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 16, 2024
    Inventors: Hidehiko KARASAKI, Shogo OKITA, Toshiyuki TAKASAKI, Ryota FURUKAWA
  • Publication number: 20240014008
    Abstract: A disclosed plasma processing apparatus 10 includes: a chamber 11 having an opening 11a; a stage 12 disposed in the chamber 11, the stage for placing an object to be processed; a dielectric member 13 closing the opening 11a; and a plasma generation unit 16 disposed on the opposite side to the chamber 11 with reference to the dielectric member 13, and configured to, when applied with a high-frequency power, generate a plasma in the chamber 11. The plasma generation unit 16 has a first coil 17 including one or a plurality of first conductors 17a connected in parallel with each other, and a second coil 18 disposed so as to surround the first coil 17 and including a plurality of second conductors 18a connected in parallel with each other. The number of the second conductors 18a is greater than the number of the first conductors 17a.
    Type: Application
    Filed: June 16, 2023
    Publication date: January 11, 2024
    Inventors: Naoaki TAKEDA, Shogo OKITA, Seiya NAGANO, Toshihiro WADA, Takahiro MIYAI
  • Patent number: 11830758
    Abstract: A plasma processing method including: a process of placing a work piece on a stage provided in a chamber, the work piece including a substrate and a holding member having an adhesive layer on a surface and holding the substrate via the adhesive layer, and having an exposed portion where the adhesive layer is exposed outside the substrate; and a plasma etching process of etching the substrate with a plasma generated in the chamber, with the exposed portion exposed to the plasma. In response to occurrence of an interruption in the plasma etching process, a cleaning process of exposing a surface of the substrate to a plasma containing an oxidizing gas is performed, and then the plasma etching process is resumed.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: November 28, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita, Akihiro Itou
  • Patent number: 11817323
    Abstract: An etching method including: a preparation step of preparing a resin layer and an electronic component supported thereby; and a resin etching step of etching the resin layer. The electronic component has a first surface covered with a protective film, a second surface opposite thereto, and a sidewall therebetween. The second surface is facing the resin layer. The resin layer is larger than the electronic component when seen from the first surface side. The resin etching step includes: a deposition step of depositing a first film, using a first plasma, on a surface of the protective film and a surface of the resin layer; and a removal step of removing, using a second plasma, the first film deposited on the resin layer and at least part of the resin layer. The deposition and removal steps are alternately repeated, with the protective film allowed to continue to exist.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: November 14, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Atsushi Harikai, Akihiro Itou
  • Patent number: 11688641
    Abstract: An element chip manufacturing method including: attaching a substrate via a die attach film (DAF) to a holding sheet; forming a protective film that covers the substrate; forming an opening in the protective film with a laser beam, to expose the substrate in the dicing region therefrom; exposing the substrate to a first plasma to etch the substrate exposed from the opening, so that a plurality of element chips are formed from the substrate and so that the DAF is exposed from the opening; exposing the substrate to a second plasma to etch the die attach film exposed from the opening, so that the DAF is split so as to correspond to the element chips; and detaching the element chips from the holding sheet, together with the split DAF. The DAF is larger than the substrate. The method includes irradiating the laser beam to the DAF protruding from the substrate.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: June 27, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hidefumi Saeki, Hidehiko Karasaki, Shogo Okita, Atsushi Harikai, Akihiro Itou
  • Patent number: 11682575
    Abstract: A plasma processing apparatus for plasma processing a substrate held on a conveying carrier, the carrier including a holding sheet and a frame supporting an outer periphery of the holding sheet. The apparatus includes a controller that controls a plasma generator, an electrostatic adsorption mechanism, and a lifting system, to sequentially execute: an adsorption step allowing the substrate to be adsorbed electrostatically to a stage; an etching step of exposing the substrate adsorbed electrostatically to the stage to an etching plasma; a frame separation step of lifting the support, to separate the frame away from the stage, with at least part of the holding sheet kept in contact with the stage; a holding sheet separation step of separating the holding sheet away from the stage; and a static elimination step of exposing the substrate separated away from the stage to a static elimination plasma.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: June 20, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita
  • Publication number: 20230170186
    Abstract: Disclosed is a plasma processing apparatus 10 including a chamber 11, a stage 12, a dielectric member 13, a cover 14, a gas introduction path 15, and an induction coil 16. The induction coil 16 includes a first induction coil 17 installed so as to overlap a central region R1 of the dielectric member 13, and a second induction coil 18 installed so as to overlap a peripheral region R2 outside the central region R1 of the dielectric member 13. The cover 14 has a first gas hole 14c formed at a position overlapping the central region R1 and a second gas hole 14d formed at a position overlapping the peripheral region R2. The gas introduction path 15 has a first gas introduction path 15a communicating with the first gas hole 14c and a second gas introduction path 15b communicating with the second gas hole 14d.
    Type: Application
    Filed: November 17, 2022
    Publication date: June 1, 2023
    Inventors: Shogo OKITA, Yoshiyuki WADA, Takahiro MIYAI, Naoaki TAKEDA, Toshihiro WADA, Toshiyuki TAKASAKI
  • Publication number: 20230114557
    Abstract: A plasma processing apparatus including: a chamber; a plasma generation unit configured to generate a plasma in the chamber; a stage 111 for placing a conveying carrier 10, the stage provided in the chamber; a cover 124 for covering at least part of the conveying carrier placed on the stage; a relative position change unit capable of changing a relative distance between the cover 124 and the stage 111 to a first distance and to a second distance smaller than the first distance; a determination unit configured to determine a placed state of the conveying carrier 10; and a control unit. The determination unit determines the placed state of the conveying carrier while the distance between the cover 124 and the stage 111 is the first distance, and the plasma processing is performed while the distance between the cover 124 and the stage 111 is the second distance.
    Type: Application
    Filed: October 3, 2022
    Publication date: April 13, 2023
    Inventors: Atsushi HARIKAI, Shogo OKITA
  • Publication number: 20230102635
    Abstract: An electronic component cleaning method including: a preparation step of preparing an electronic component having a first surface covered with a protective film, a second surface opposite to the first surface, a sidewall between the first and second surfaces, and an adhering matter adhering to the sidewall; and a sidewall cleaning step of cleaning the sidewall. The sidewall cleaning step includes a deposition step of depositing a first film on the protective film and a surface of the adhering matter, using a first plasma, and a removal step of removing the first film deposited on the surface of the adhering matter, together with at least part of the adhering matter, using a second plasma. In the sidewall cleaning step, the deposition step and the removal step are alternately repeated a plurality of times, so as to allow the protective film to continue to exist.
    Type: Application
    Filed: December 4, 2020
    Publication date: March 30, 2023
    Inventors: Shogo OKITA, Akihiro ITOU, Atsushi HARIKAI
  • Patent number: 11551974
    Abstract: A manufacturing process of an element chip comprises a preparing step for preparing a substrate having first and second sides opposed to each other, the substrate containing a semiconductor layer, a wiring layer and a resin layer formed on the first side, and the substrate including a plurality of dicing regions and element regions defined by the dicing regions. Also, the manufacturing process comprises a laser grooving step for irradiating a laser beam onto the dicing regions to form grooves so as to expose the semiconductor layer along the dicing regions. Further, the manufacturing process comprises a dicing step for plasma-etching the semiconductor layer along the dicing regions through the second side to divide the substrate into a plurality of the element chips. The laser grooving step includes a melting step for melting a surface of the semiconductor layer exposed along the dicing regions.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: January 10, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hidefumi Saeki, Atsushi Harikai, Shogo Okita
  • Publication number: 20220402072
    Abstract: An element chip manufacturing method includes a step of preparing a substrate including a semiconductor layer and a wiring layer formed on the semiconductor layer, the substrate having element regions and a dicing region defining the element regions, a laser grooving step of irradiating a laser beam to the wiring layer at the dicing region, to form an aperture exposing the semiconductor layer, and a step of etching the semiconductor layer exposed from the aperture, with plasma, to divide the substrate into a plurality of element chips. The laser grooving step includes a step of irradiating a first laser beam having a first pulse width, to remove the wiring layer in an edge portion of the dicing region, and a step of irradiating a second laser beam having a second pulse width which is longer than the first pulse width, to remove the wiring layer inside from the edge portion.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 22, 2022
    Inventors: Hidefumi SAEKI, Hidehiko KARASAKI, Shogo OKITA, Atsushi HARIKAI, Akihiro ITOU
  • Publication number: 20220406660
    Abstract: An element chip manufacturing method includes a step of preparing a substrate including a semiconductor layer and a wiring layer formed on the semiconductor layer and having a plurality of element regions and a dicing region defining the element regions, a laser grooving step of irradiating a laser beam to the wiring layer at the dicing region, to form an aperture exposing the semiconductor layer, and an individualization step of etching the semiconductor layer exposed from the aperture, with plasma, to divide the substrate into a plurality of element chips. The laser grooving step including a step of irradiating a first laser beam, to form a first groove exposing the semiconductor layer in the dicing region, and a step of irradiating a second laser beam, with a beam center positioned outside a side wall of the first groove, to widen the first groove into the aperture.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 22, 2022
    Inventors: Shogo OKITA, Hidehiko KARASAKI, Hidefumi SAEKI, Atsushi HARIKAI
  • Publication number: 20220384177
    Abstract: A method including: a step of preparing a substrate that includes a first layer having a first principal surface provided with a dicing region, and a mark, and a second principal surface, and includes a semiconductor layer; a step of covering a first region corresponding to the mark on the second principal surface, with a resist film; a step of forming a metal film on the second principal surface; a step of removing the resist film, to expose the semiconductor layer corresponding to the first region; a step of imaging the substrate, with a camera, to detect a position of the mark through the semiconductor layer, and calculating a second region corresponding to the dicing region on a surface of the metal film; and a step of irradiating a laser beam to the second region, to remove the metal film and expose the semiconductor layer corresponding to the second region.
    Type: Application
    Filed: May 16, 2022
    Publication date: December 1, 2022
    Inventors: Hidehiko KARASAKI, Shogo OKITA
  • Publication number: 20220367273
    Abstract: A method including: a step of preparing a substrate that includes a first layer having a dicing region and a mark, and including a semiconductor layer, and a second layer including a metal film; a step of removing the metal film, to expose the semiconductor layer corresponding to a first region that corresponds to the mark; a step of smoothing a surface of the exposed semiconductor layer; a step of imaging the substrate, with a camera sensing predetermined electromagnetic waves, to detect a position of the mark through the semiconductor layer, and calculating a second region corresponding to the dicing region; and a step of removing the metal film, to expose the semiconductor layer corresponding to the second region. In the smoothing step, the surface of the semiconductor layer is smoothed so as to have a surface roughness of 1/4 or less of a wavelength of the predetermined electromagnetic waves.
    Type: Application
    Filed: May 2, 2022
    Publication date: November 17, 2022
    Inventors: Hidehiko KARASAKI, Shogo OKITA
  • Publication number: 20220262603
    Abstract: A dry etching apparatus plasma processes a wafer held by a carrier having a frame and an holding sheet. The carrier is placed on an electrode unit of a stage provided in a chamber. The electrode unit is cooled by a cooling section configured to cool the electrode unit. An upper face of the electrode unit is at least as large as the back side of the carrier. The holding sheet and the frame are cooled effectively by the heat transfer to the stage.
    Type: Application
    Filed: May 5, 2022
    Publication date: August 18, 2022
    Inventor: Shogo OKITA
  • Patent number: 11398372
    Abstract: A plasma processing apparatus that performs plasma processing to a substrate held on a transport carrier including a frame and a holding sheet that covers an opening of the frame includes: a transport mechanism that transports the transport carrier; a position measuring section that measures a position of the substrate to the frame; a plasma processing section that includes a plasma processing stage on which the transport carrier is loaded and a cover that covers the frame and a part of the holding sheet loaded on the plasma processing stage, and has a window section for exposing a part of the substrate; and a control section that controls the transport mechanism such that the transport carrier is loaded on the plasma processing stage to satisfy a positional relationship between the window section and the substrate based on the position information of the substrate to the frame.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: July 26, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Hiromi Asakura, Syouzou Watanabe, Noriyuki Matsubara, Mitsuru Hiroshima, Toshihiro Wada
  • Publication number: 20220199411
    Abstract: Disclosed is a method for producing element chips. The method includes: a preparing step of preparing a substrate 10 that is held on a holding sheet 22 that is supported by a frame 21, the substrate including element regions and dicing regions; a protective film forming step of forming a protective film 15 so as to cover the frame 21, the holding sheet 22, and the substrate 10; a patterning step of removing a part of the protective film 15 so as to expose the dicing regions of the substrate 10; a plasma dicing step including a process that uses a plasma that contains fluorine, the plasma dicing step being a step of individualizing the substrate 10 into a plurality of element chips; and a fluorine removing step of removing, together with the protective film 15, fluorine attached to the protective film 15 in the plasma dicing step.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 23, 2022
    Inventors: Toshiyuki TAKASAKI, Ryota FURUKAWA, Atsushi HARIKAI, Shogo OKITA
  • Patent number: 11361944
    Abstract: A plasma processing method, including: a trenched substrate preparation process of preparing a trenched substrate having trenches having a bottom exposing an oxide film; and an oxide film removal process of exposing the trenched substrate to a plasma, to remove the oxide film. The oxide film removal process includes a plurality of cycles, each cycle including: an oxide film etching step of etching the oxide film; and a cleaning step of removing an attached matter on inner walls of the trenches, after the oxide film etching step.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: June 14, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita
  • Publication number: 20220181188
    Abstract: A plasma processing method including: a process of placing a work piece on a stage provided in a chamber, the work piece including a substrate and a holding member having an adhesive layer on a surface and holding the substrate via the adhesive layer, and having an exposed portion where the adhesive layer is exposed outside the substrate; and a plasma etching process of etching the substrate with a plasma generated in the chamber, with the exposed portion exposed to the plasma. In response to occurrence of an interruption in the plasma etching process, a cleaning process of exposing a surface of the substrate to a plasma containing an oxidizing gas is performed, and then the plasma etching process is resumed.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 9, 2022
    Inventors: Atsushi Harikai, Shogo Okita, Akihiro Itou
  • Publication number: 20220181209
    Abstract: The element chip manufacturing method includes: a preparing process of preparing a substrate 1 including a plurality of element regions EA and a dividing region DA, the substrate 1 having a first principal surface 1X and a second principal surface 1Y; a groove forming process of forming a groove 13 in the dividing region DA from the first principal surface 1X side; and a grinding process of grinding the substrate 1 from the second principal surface 1Y side, to divide the substrate 1 into a plurality of element chips 20. The groove 13 includes a first region 13a constituted by a side surface having a first surface roughness, and a second region 13b constituted by a side surface having a second surface roughness larger than the first surface roughness. In the grinding process, grinding of the substrate 1 is performed until reaching the first region 13a of the groove 13.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 9, 2022
    Inventors: Atsushi HARIKAI, Shogo OKITA, Akihiro ITOU, Toshiyuki TAKASAKI