Patents by Inventor Shogo Okita

Shogo Okita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200381367
    Abstract: An element chip manufacturing method including: preparing a semiconductor substrate including a first layer having a first principal surface, and a second layer having a second principal surface, the first layer provided with element regions, a dicing region, and an alignment mark, wherein the first layer includes a semiconductor layer, and the second layer includes a metal layer adjacent to the semiconductor layer; irradiating a first laser beam absorbed in the metal film and passing through the semiconductor layer, from the second principal surface side to a first region corresponding to the mark; imaging the semiconductor substrate from the second principal surface side with a camera, and then calculating a second region corresponding to the dicing region on the second principal surface; irradiating a second laser beam to the second region from the second principal surface side; and dicing the semiconductor substrate into a plurality of element chips.
    Type: Application
    Filed: May 12, 2020
    Publication date: December 3, 2020
    Inventors: Kiyoshi ARITA, Shogo OKITA, Hidehiko KARASAKI
  • Publication number: 20200357654
    Abstract: A manufacturing process of an element chip comprises steps of preparing a substrate including a plurality of etching regions and element regions each containing a plurality of convex and concave portions, holding the substrate and a frame with a holding sheet, forming a protective film by applying a first mixture to form a coated film above the substrate and by drying the coated film to form the protective film along the convex and concave portions, the first mixture containing a water-soluble first resin, water and a water-soluble organic solvent and has a vapor pressure higher than water, removing the protective film by irradiating a laser beam thereon to expose the substrate in the etching regions, plasma-etching the substrate along the etching regions while maintaining the protective film in the element regions to individualize the substrate, and removing the protective film by contacting the protective film with an aqueous rinse solution.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Atsushi HARIKAI, Noriyuki MATSUBARA, Shogo OKITA, Hidehiko KARASAKI
  • Patent number: 10818553
    Abstract: The method for manufacturing an element chip includes: sticking an adhesive tape having translucency to a front surface of a semiconductor wafer; measuring a position and a width of a second close contact portion in a dividing region; applying a laser beam having a beam diameter smaller than the width of the second close contact portion to the adhesive tape such that the laser beam does not protrude from the second close contact portion based on the width of the second close contact portion and the beam diameter, and forming an exposed portion; exposing the front surface to plasma with a back surface held by a dicing tape, and while protecting an element region from the plasma with an adhesive tape, etching the dividing region exposed in the exposed portion to dice the substrate into a plurality of element chips; and removing the adhesive tape remaining on the front surface.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: October 27, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Shogo Okita
  • Publication number: 20200294791
    Abstract: An element chip manufacturing method including: a preparing step of preparing a substrate including a plurality of element regions and a dicing region defining the element regions, the substrate having a first surface and a second surface opposite the first surface; a laser scribing step of applying a laser beam to the dicing region from a side of the first surface, to form a groove corresponding to the dicing region and being shallower than a thickness of the substrate; a cleaning step of exposing the first surface of the substrate to a first plasma, to remove debris on the groove; and a dicing step of exposing the substrate at a bottom of the groove to a second plasma after the cleaning step, to dice the substrate into element chips including the element regions. The first plasma is generated from a process gas containing a carbon oxide gas.
    Type: Application
    Filed: March 5, 2020
    Publication date: September 17, 2020
    Inventors: Shogo OKITA, Atsushi HARIKAI, Akihiro ITOU
  • Patent number: 10763124
    Abstract: A manufacturing process of an element chip comprises steps of preparing a substrate including a plurality of dicing regions and element regions each containing a plurality of convex and concave portions, holding the substrate and a frame with a holding sheet, forming a protective film by applying a first mixture to form a coated film above the substrate and by drying the coated film to form the protective film along the convex and concave portions, the first mixture containing a first resin and an organic solvent having a vapor pressure higher than water, removing the protective film by irradiating a laser beam thereon to expose the substrate in the dicing regions, plasma-etching the substrate along the dicing regions while maintaining the protective film in the element regions to individualize the substrate, and removing the protective film by contacting the protective film with an aqueous rinse solution.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: September 1, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Noriyuki Matsubara, Shogo Okita, Hidehiko Karasaki
  • Patent number: 10714356
    Abstract: Provided is a plasma processing method which comprises steps of preparing a conveying carrier including a holding sheet and a frame provided on a peripheral region of the holding sheet, adhering the substrate on the holding sheet in an inner region inside the peripheral region to hold the substrate on the conveying carrier, sagging the holding sheet in the inner region, setting the conveying carrier on a stage provided within a plasma processing apparatus to contact the holding sheet on the stage so that the holding sheet in the inner region touches the stage before the holding sheet in the peripheral region does, and plasma processing the substrate.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: July 14, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Atsushi Harikai, Akihiro Itou, Noriyuki Matsubara
  • Publication number: 20200098636
    Abstract: An element chip manufacturing method including: a preparing step of preparing a first conveying carrier including a holding sheet and a frame, and a substrate held on the holding sheet, the holding sheet having a first surface and a second surface opposite the first surface, the frame attached to at least part of a peripheral edge of the holding sheet; a placing step of placing the first conveying carrier holding the substrate, on a second conveying carrier; a preprocessing step of preprocessing the substrate, after the placing step; a removing step of removing the second conveying carrier, after the preprocessing step; and a dicing step of subjecting the substrate held on the first conveying carrier to plasma exposure, after the removing step, to form a plurality of element chips from the substrate.
    Type: Application
    Filed: September 11, 2019
    Publication date: March 26, 2020
    Inventors: Atsushi HARIKAI, Shogo OKITA, Noriyuki MATSUBARA, Hidefumi SAEKI, Akihiro ITOU
  • Publication number: 20190371668
    Abstract: A substrate has first and second surfaces, and includes a plurality of element regions and dividing region defining the element regions. An method for manufacturing an element chip includes: a protective film formation step of applying a mixture containing a water-soluble resin and a solvent to the first surface, to form a protective film; a laser grooving step of irradiating, with laser light, portions of the protective film covering the dividing regions, to remove these portions, and expose the first surface in the dividing regions; a step of dicing the substrate into element chips by plasma etching the substrate in the dividing regions; and a step of removing the portions of the protective film. The resin has melting point of 250° C. or more, or decomposition temperature of 450° C. or more, and the protective film has absorption coefficient of 1 abs·L/g·cm?1 or more for wavelength of the laser light.
    Type: Application
    Filed: May 30, 2019
    Publication date: December 5, 2019
    Inventors: Hidehiko KARASAKI, Shogo OKITA, Noriyuki MATSUBARA, Atsushi HARIKAI
  • Publication number: 20190371669
    Abstract: A substrate has first and second surfaces, and includes a plurality of element regions and dividing region defining the element regions. A method for manufacturing an element chip includes: a step of spray coating, to the first surface of the substrate, a mixture containing a water-soluble resin and an organic solvent having a higher vapor pressure than water, and drying the coated mixture at a temperature of 50° C. or less, to form a protective film; a laser grooving step of removing portions of the protective film covering the dividing regions; a step of dicing the substrate into element chips by plasma etching the substrate; and a step of removing the portions of the protective film covering the element regions. The mixture has a solid component ratio of 200 g/L or more, and droplets of the sprayed mixture have an average particle size of 12 ?m or less.
    Type: Application
    Filed: May 30, 2019
    Publication date: December 5, 2019
    Inventors: Hidehiko KARASAKI, Shogo OKITA, Noriyuki MATSUBARA, Hidefumi SAEKI
  • Patent number: 10497622
    Abstract: A semiconductor chip manufacturing method includes preparing a semiconductor wafer including a front surface on which a bump is exposed, a rear surface located at a side opposite to the front surface, a plurality of element regions in each of which the bump is formed, and a dividing region defining each of the element regions, forming a mask which covers the bump and has an opening exposing the dividing region on the surface of the semiconductor wafer by spraying liquid which contains raw material of the mask along the bump by a spray coating method, and singulating the semiconductor wafer by exposing the surface of the semiconductor wafer to first plasma and etching the dividing region, which is exposed to the opening, until the rear surface is reached in a state where the bump is covered by the mask.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: December 3, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Mitsuru Hiroshima, Atsushi Harikai, Noriyuki Matsubara, Akihiro Itou
  • Patent number: 10475704
    Abstract: In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate having a plurality of element regions, the substrate is divided into element chips 10 by exposing the substrate to a first plasma. Therefore, element chips having a first surface, a second surface, and a side surface connecting the first surface and the second surface are held spaced from each other on a carrier. A protection film covering the element chip is formed only on the side surface and it is possible to suppress creep-up of a conductive material to the side surface in the mounting step by exposing the element chips to second plasma in which a mixed gas of fluorocarbon and helium is used as a raw material gas.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: November 12, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita, Noriyuki Matsubara, Mitsuru Hiroshima, Mitsuhiro Okune
  • Publication number: 20190304838
    Abstract: A manufacturing process of an element chip comprises a preparing step for preparing a substrate having first and second sides opposed to each other, the substrate containing a semiconductor layer, a wiring layer and a resin layer formed on the first side, and the substrate including a plurality of dicing regions and element regions defined by the dicing regions. Also, the manufacturing process comprises a laser grooving step for irradiating a laser beam onto the dicing regions to form grooves so as to expose the semiconductor layer along the dicing regions. Further, the manufacturing process comprises a dicing step for plasma-etching the semiconductor layer along the dicing regions through the second side to divide the substrate into a plurality of the element chips. The laser grooving step includes a melting step for melting a surface of the semiconductor layer exposed along the dicing regions.
    Type: Application
    Filed: March 25, 2019
    Publication date: October 3, 2019
    Inventors: Hidefumi SAEKI, Atsushi HARIKAI, Shogo OKITA
  • Publication number: 20190295894
    Abstract: The method for manufacturing an element chip includes: sticking an adhesive tape having translucency to a front surface of a semiconductor wafer; measuring a position and a width of a second close contact portion in a dividing region; applying a laser beam having a beam diameter smaller than the width of the second close contact portion to the adhesive tape such that the laser beam does not protrude from the second close contact portion based on the width of the second close contact portion and the beam diameter, and forming an exposed portion; exposing the front surface to plasma with a back surface held by a dicing tape, and while protecting an element region from the plasma with an adhesive tape, etching the dividing region exposed in the exposed portion to dice the substrate into a plurality of element chips; and removing the adhesive tape remaining on the front surface.
    Type: Application
    Filed: February 20, 2019
    Publication date: September 26, 2019
    Inventor: Shogo OKITA
  • Patent number: 10424488
    Abstract: The yield of a product is improved when a substrate held by a conveyance carrier is subjected to a plasma treatment. A method of manufacturing an electronic component includes preparing a substrate which is bonded to a holding sheet of a conveyance carrier, the conveyance carrier including the holding sheet and a frame disposed on an outer peripheral portion of the holding sheet, the substrate having a circuit layer; heating the holding sheet after preparing the substrate; cooling the holding sheet after heating the holding sheet; and plasma etching the substrate to singulate the substrate into the electronic component in a state that the substrate is placed above a stage included in a plasma treatment apparatus and the substrate is in contact with the stage via the holding sheet.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: September 24, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Atsushi Harikai
  • Patent number: 10361111
    Abstract: Provided is a plasma processing apparatus which comprises a chamber, a stage configured to set a holding sheet and a substrate held thereon, a securing mechanism configured to secure the holding sheet on the stage, a plasma generator including a first electrode and a first high-frequency power supply, and a determiner for determining a contact status between the holding sheet and the stage, wherein a gas through-hole is arranged on a surface of the stage in an annular region defined between an inner edge of a frame set on the stage and an outer edge of the substrate, and wherein the determiner is configured to determine the contact status in accordance with a pressure of a gas in the gas introduction conduit and/or a regulation data for regulating the pressure of the gas, the gas being introduced between the stage and the holding sheet from the gas through-hole.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: July 23, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Takahiro Miyai
  • Publication number: 20190221479
    Abstract: A manufacturing process of an element chip comprises steps of preparing a substrate including dicing regions and element regions, attaching a holding sheet held on a frame with a die attach film in between, forming a protective film covering the substrate, forming a plurality of grooves in the protective film along the dicing regions, plasma-etching the substrate to expose the die attach film and then die attach film along the dicing regions, and picking up each of the element chips along with the separated die attach film away from the holding sheet, wherein the die attach film has an area greater than that of the substrate, and wherein the protective film includes a first covering portion covering the substrate and a second covering portion covering at least a portion of the die attach film that extends beyond an outer edge of the substrate.
    Type: Application
    Filed: January 14, 2019
    Publication date: July 18, 2019
    Inventors: Shogo OKITA, Atsushi HARIKAI, Noriyuki MATSUBARA, Hidefumi SAEKI, Akihiro ITOU
  • Publication number: 20190157100
    Abstract: A manufacturing process of an element chip comprises steps of preparing a substrate including a plurality of dicing regions and element regions each containing a plurality of convex and concave portions, holding the substrate and a frame with a holding sheet, forming a protective film by applying a first mixture to form a coated film above the substrate and by drying the coated film to form the protective film along the convex and concave portions, the first mixture containing a first resin and an organic solvent having a vapor pressure higher than water, removing the protective film by irradiating a laser beam thereon to expose the substrate in the dicing regions, plasma-etching the substrate along the dicing regions while maintaining the protective film in the element regions to individualize the substrate, and removing the protective film by contacting the protective film with an aqueous rinse solution.
    Type: Application
    Filed: November 19, 2018
    Publication date: May 23, 2019
    Inventors: Atsushi HARIKAI, Noriyuki Matsubara, Shogo Okita, Hidehiko Karasaki
  • Patent number: 10297489
    Abstract: A plasma processing method includes a mounting process of mounting a holding sheet holding a substrate in a stage provided in a plasma processing apparatus, and a fixing process of fixing the holding sheet to the stage. The plasma processing method further includes a determining process of determining whether or not a contact state of the holding sheet with the stage is good or bad after the fixing process, and a plasma etching process of etching the substrate by exposing a surface of the substrate to plasma on the stage, in a case in which the contact state is determined to be good in the determining process.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: May 21, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Atsushi Harikai, Akihiro Itou
  • Patent number: 10297487
    Abstract: Provided is a method of manufacturing a semiconductor chip, the method comprising: preparing a plurality of semiconductor chips, each of which has a surface to which a BG tape is stuck, and a rear surface to which a DAF is stuck, and which are held spaced from each other by the BG tape and the DAF, exposing the DAF between semiconductor chips that are adjacent to each other when viewed from the surface side, by stripping the BG tape from the surface of each of the plurality of semiconductor chips, etching the DAF that is exposed between the semiconductor chips that are adjacent to each other, by irradiating the plurality of semiconductor chips held on the DAF, with plasma.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: May 21, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Atsushi Harikai, Noriyuki Matsubara, Akihiro Itou
  • Patent number: 10276423
    Abstract: A method of manufacturing a semiconductor chip includes: preparing a semiconductor wafer; forming a mask on a front surface of the semiconductor wafer so as to cover each of the element regions and to expose the dividing region; exposing the front surface to plasma in a state where a back surface of the semiconductor wafer is held with a dicing tape to dice the semiconductor wafer into a plurality of semiconductor chips by etching the dividing region exposed from the mask up to the back surface while protecting each of the element regions with the mask from plasma; and removing the mask from the front surface together with an adhesive tape by peeling off the adhesive tape after sticking the adhesive tape to the side of the front surface.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: April 30, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Koji Tamura, Akihiro Itou, Atsushi Harikai, Noriyuki Matsubara