Abstract: A multiple-word multiplication-accumulation circuit suitable for use with a single-port memory. The circuit is composed of a multiplication-accumulation (MAC) operator and surrounding registers. The MAC operator has multiplicand and multiplier input ports with different bit widths to calculate a sum of products of multiple-word data read out of a memory. The registers serve as buffer storage of multiple-word data to be supplied to individual input ports of the MAC operator. The amount of data supplied to the MAC operator in each clock cycle is adjusted such that total amount of data consumed and produced by the MAC operator in one clock cycle will be equal to or smaller than the maximum amount of data that the memory can transfer in one clock cycle. This feature enables the use of a bandwidth-limited single-port memory, without causing adverse effect on the efficiency of MAC operator usage.

Abstract: To provide a method of measuring a position of a node by using a radio communication system which comprises the node to send a position measuring signal, and a plurality of base stations to receive radio signals from the node, the method including: the base stations watching signals from the node through a predetermined channel; at least one of the base stations sending a reference signal after receiving of the position measuring signal; at least two of the base stations measuring the reception timing of the position measuring signal and the reception timing of the reference signal; and calculating the position of the node by using the reception timing of the position measuring signal and the reference signal measured by the base stations which have received the reference signal, and position information of the base station which has received the position measuring signal.

Abstract: An electronic tag comprises a unit for storing transmission-use data and a unit for both comparing between the stored data and comparison data sent from an R/W and for determining whether or not the identifier of the tag per se is to be transmitted to the R/W in order to participate in an anti-collision process carried out between the electronic tag and the R/W as a necessary process prior to transmitting data to the R/W for the purpose of speeding up the recognition of electronic tags retaining data satisfying a condition by making the electronic tags retaining data satisfying the condition, from among a large number of electronic tags, participate in the anti-collision process.

Abstract: An arithmetic device for Montgomery modular multiplication which quickly calculates a parameter ND, the parameter ND satisfying R×R?1?N×ND=1 for an integer N and a radix R that is coprime to and greater than N, with a large number of effective lower bits. The device comprises an ND generator, a multiplication-accumulation (MAC) operator, and a sum data store. The ND generator produces effective lower bits of ND at a rate of k bits per clock cycle, with reference to lower k bits of a variable S, as well as to lower k bits of an odd positive integer N. The MAC operator multiplies the produced k-bit ND value by N and adds the resulting product to S. The sum data store stores the variable S, which is updated with the output of the MAC operator, with its bits shifted right by k bits, for use by the ND generator in the subsequent clock cycle.

Abstract: For a predetermined period from the start of a read operation, an electric current is fed to bit lines connected with memory cells so that ferroelectric capacitors of the memory cells are charged. The voltage change of the bit lines are different according to the logic values of data stored in the ferroelectric capacitors. Therefore, the logic value stored in the memory cells can be detected as a time difference. Even if the voltage change of the bit lines is small, the time difference can be reliably generated. Even in case the residual dielectric polarization value of the ferroelectric capacitor is low, therefore, the data can be reliably read from the memory cells. In short, the read margin of data can be better improved than in the case where the logic value of data is detected with a voltage difference.

Abstract: An integrated circuit has a sleep switch, provided between a first power line and a second power line, which is constituted by a transistor of a first threshold voltage, and which becomes non-conducting in a sleep mode, and further has a latch circuit, connected to the second power line, which is constituted by a transistor of a second threshold voltage which is lower than the first threshold voltage, and a ferroelectric capacitor for storing data held in the latch circuit in accordance with the polarization direction of a ferroelectric film thereof. The integrated circuit also comprises a control signal generating circuit which, when returning to an active mode from the sleep mode, generates a plate signal for driving a terminal of the ferroelectric capacitor to generate a voltage in the latch circuit in accordance with the polarization direction, and generates a sleep signal for causing the sleep switch to conduct to thereby activate the latch circuit following the driving of the ferroelectric capacitor.

Abstract: For a predetermined period from the start of a read operation, an electric current is fed to bit lines connected with memory cells so that ferroelectric capacitors of the memory cells are charged. The voltage change of the bit lines are different according to the logic values of data stored in the ferroelectric capacitors. Therefore, the logic value stored in the memory cells can be detected as a time difference. Even if the voltage change of the bit lines is small, the time difference can be reliably generated. Even in case the residual dielectric polarization value of the ferroelectric capacitor is low, therefore, the data can be reliably read from the memory cells. In short, the read margin of data can be better improved than in the case where the logic value of data is detected with a voltage difference.

Abstract: An information processing apparatus receives a carrier wave modulated in accordance with information and extracts the information and power therefrom to execute a given process. A receiving circuit receives the carrier wave. A dc power generating circuit rectifies the carrier wave received by the receiving circuit to thereby generate dc power. A demodulation circuit is structurally independent of the dc power generating circuit, and retrieves the information modulated onto the carrier wave. An information processing circuit is supplied with the dc power as a power source, and processes the information retrieved by the demodulation circuit in a given manner. Since the demodulation circuit and the dc power generating circuit are structurally independent of each other, interference between elements included in these circuits can be eliminated and simple designing is enabled. In addition, power consumed in the apparatus can be reduced because of optimal designing.

Abstract: A nonvolatile data storage circuit has a data holding circuit having a storage node, and a plurality of ferroelectric capacitors one electrodes of which are connected to the storage node. In this nonvolatile data storage circuit, in store operations to write data from the data holding circuit to the ferroelectric capacitors, the timing of at least the rising or the falling of plate signals supplied to the other electrodes of the plurality of ferroelectric capacitors, is made different. During store operation, the timing of the plate signals applied to the plurality of ferroelectric capacitors connected to the storage node is shifted, so that coupling noise between the ferroelectric capacitors is dispersed and can be reduced, and data inversion of the data holding circuit can be prevented.

Abstract: Memory cells each include a latch having storage nodes of data, and ferroelectric capacitors connected to the storage nodes at one ends, respectively, and to a plate line at the other ends. An operation control circuit performs volatile and nonvolatile write operations. A plate driver sets the plate line at a predetermined voltage so that a voltage exceeding a coercive voltage is applied between electrodes of the ferroelectric capacitor connected to either one end of the latch during the volatile write operation. Here, the latch retains the write data. It is therefore possible to dispense with a circuit generating a voltage lower than or equal to the coercive voltage and a circuit for switching voltages. This also eliminates the need for power supply line of the voltage lower than or equal to the coercive voltage, making the wiring area unnecessary. Consequently, the ferroelectric memory can be reduced in chip size.

Abstract: A programmable logic device with ferroelectric configuration memories storing multiple configuration data sets. The device has programmable logic blocks, interconnections, and I/O blocks to provide desired logic functions. Those building blocks can be dynamically reconfigured by changing the selection of configuration data stored in the device's integral configuration memories. The configuration memories are divided into groups, so that they can be loaded concurrently with multiple configuration data streams. To protect the content of configuration memories from unauthorized access, the device employs an authentication mechanism that uses security IDs stored in the configuration memories. The device has a memory controller to provide an appropriate power supply sequence for ferroelectric memory cells to ensure the reliable data retention when the device is powered up or shut down.

Abstract: A multiple-word multiplication-accumulation circuit suitable for use with a single-port memory. The circuit is composed of a multiplication-accumulation (MAC) operator and surrounding registers. The MAC operator has multiplicand and multiplier input ports with different bit widths to calculate a sum of products of multiple-word data read out of a memory. The registers serve as buffer storage of multiple-word data to be supplied to individual input ports of the MAC operator. The amount of data supplied to the MAC operator in each clock cycle is adjusted such that total amount of data consumed and produced by the MAC operator in one clock cycle will be equal to or smaller than the maximum amount of data that the memory can transfer in one clock cycle. This feature enables the use of a bandwidth-limited single-port memory, without causing adverse effect on the efficiency of MAC operator usage.

Abstract: An arithmetic device for Montgomery modular multiplication which quickly calculates a parameter ND with a large number of effective lower bits. The device comprises an ND generator, a multiplication-accumulation (MAC) operator, and a sum data store. The ND generator produces effective lower bits of ND at a rate of k bits per clock cycle, with reference to lower k bits of a variable S, as well as to lower k bits of an odd positive integer N. The MAC operator multiplies the produced k-bit ND value by N and adds the resulting product to S. The sum data store stores the variable S, which is updated with the output of the MAC operator, with its bits shifted right by k bits, for use by the ND generator in the subsequent clock cycle.

Abstract: To provide a method of measuring a position of a node by using a radio communication system which comprises the node to send a position measuring signal, and a plurality of base stations to receive radio signals from the node, the method including: the base stations watching signals from the node through a predetermined channel; at least one of the base stations sending a reference signal after receiving of the position measuring signal; at least two of the base stations measuring the reception timing of the position measuring signal and the reception timing of the reference signal; and calculating the position of the node by using the reception timing of the position measuring signal and the reference signal measured by the base stations which have received the reference signal, and position information of the base station which has received the position measuring signal.

Abstract: Upon reading data from a memory cell, first and second bit lines are precharged beforehand at a grounding voltage. Then, at a start of the reading, a predetermined amount of direct-current bias electricity is supplied to the first and second bit lines for a predetermined period of time by a direct-current bias electricity supply circuit. Thereafter, a sense amplifier is activated.

Abstract: Memory cells each include a latch having storage nodes of data, and ferroelectric capacitors connected to the storage nodes at one ends, respectively, and to a plate line at the other ends. An operation control circuit performs volatile and nonvolatile write operations. A plate driver sets the plate line at a predetermined voltage so that a voltage exceeding a coercive voltage is applied between electrodes of the ferroelectric capacitor connected to either one end of the latch during the volatile write operation. Here, the latch retains the write data. It is therefore possible to dispense with a circuit generating a voltage lower than or equal to the coercive voltage and a circuit for switching voltages. This also eliminates the need for power supply line of the voltage lower than or equal to the coercive voltage, making the wiring area unnecessary. Consequently, the ferroelectric memory can be reduced in chip size.

Abstract: A rectifier circuit converts an alternating current into a direct-current voltage and outputs it as a power supply voltage. A ferroelectric holding circuit has a volatile holding circuit and a plurality of ferroelectric capacitors. Data held in the ferroelectric holding circuit has a read margin greater than that of data held in ferroelectric memory cells in a memory array. The ferroelectric holding circuit thus operates with reliability even if power that the semiconductor integrated circuit receives is low. Consequently, since the ferroelectric holding circuit is formed on the semiconductor integrated circuit to be implemented on an RFID transponder or a non-contact IC card, the communication range between the RFID transponder or non-contact IC card and a reader/writer can be extended.

Abstract: An integrated circuit has a sleep switch, provided between a first power line and a second power line, which is constituted by a transistor of a first threshold voltage, and which becomes non-conducting in a sleep mode, and further has a latch circuit, connected to the second power line, which is constituted by a transistor of a second threshold voltage which is lower than the first threshold voltage, and a ferroelectric capacitor for storing data held in the latch circuit in accordance with the polarization direction of a ferroelectric film thereof. The integrated circuit also comprises a control signal generating circuit which, when returning to an active mode from the sleep mode, generates a plate signal for driving a terminal of the ferroelectric capacitor to generate a voltage in the latch circuit in accordance with the polarization direction, and generates a sleep signal for causing the sleep switch to conduct to thereby activate the latch circuit following the driving of the ferroelectric capacitor.

Abstract: A nonvolatile data storage circuit has a data holding circuit having a storage node, and a plurality of ferroelectric capacitors one electrodes of which are connected to the storage node. In this nonvolatile data storage circuit, in store operations to write data from the data holding circuit to the ferroelectric capacitors, the timing of at least the rising or the falling of plate signals supplied to the other electrodes of the plurality of ferroelectric capacitors, is made different. During store operation, the timing of the plate signals applied to the plurality of ferroelectric capacitors connected to the storage node is shifted, so that coupling noise between the ferroelectric capacitors is dispersed and can be reduced, and data inversion of the data holding circuit can be prevented.

Abstract: Upon reading data from a memory cell, first and second bit lines are precharged beforehand at a grounding voltage. Then, at a start of the reading, a predetermined amount of direct-current bias electricity is supplied to the first and second bit lines for a predetermined period of time by a direct-current bias electricity supply circuit. Thereafter, a sense amplifier is activated.