Patents by Inventor Shoichiro Kasahara

Shoichiro Kasahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10742169
    Abstract: An oscillator includes a resonator and an integrated circuit element. The resonator includes a resonator element and a resonator element container accommodating the resonator element. The integrated circuit element includes an inductor. The resonator and the integrated circuit element are stacked on each other. The resonator includes a metal member, and the metal member does not overlap the inductor when viewed in a plan view.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: August 11, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Hisahiro Ito, Tetsuya Otsuki, Shoichiro Kasahara
  • Publication number: 20190165732
    Abstract: An oscillator includes a resonator and an integrated circuit element. The resonator includes a resonator element and a resonator element container accommodating the resonator element. The integrated circuit element includes an inductor. The resonator and the integrated circuit element are stacked on each other. The resonator includes a metal member, and the metal member does not overlap the inductor when viewed in a plan view.
    Type: Application
    Filed: November 26, 2018
    Publication date: May 30, 2019
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hisahiro ITO, Tetsuya OTSUKI, Shoichiro KASAHARA
  • Patent number: 9984991
    Abstract: In order to reduce crosstalk between analog and digital signals, a circuit device includes a vibrator element, a semiconductor device, and a package. In the semiconductor device, an analog pad is provided along a first side facing in a first direction when the semiconductor device is seen in plan view. In addition, a digital pad is provided along aside facing in a second direction opposite to the first direction, that is, a second side facing the first side. In the package, an analog terminal which is connected to the analog pad is provided on a first side of the package facing in the first direction. In addition, a digital terminal which is connected to the digital pad is provided on a second side of the package facing in the second direction.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: May 29, 2018
    Assignee: Seiko Epson Corporation
    Inventors: Hisahiro Ito, Shoichiro Kasahara
  • Patent number: 9564875
    Abstract: In order to achieve a circuit device capable of stably supplying an antenna with electric power in a broad power range to output a transmission signal, the circuit device includes a current source adapted to supply a first current in a first operation mode, and supply a second current higher than the first current in a second operation mode, and a drive section supplied with the electric power from the current source, and adapted to perform drive for outputting a transmission signal to an antenna via a matching circuit.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: February 7, 2017
    Assignee: Seiko Epson Corporation
    Inventors: Minoru Kozaki, Shoichiro Kasahara
  • Publication number: 20160020379
    Abstract: In order to reduce crosstalk between analog and digital signals, a circuit device includes a vibrator element, a semiconductor device, and a package. In the semiconductor device, an analog pad is provided along a first side facing in a first direction when the semiconductor device is seen in plan view. In addition, a digital pad is provided along aside facing in a second direction opposite to the first direction, that is, a second side facing the first side. In the package, an analog terminal which is connected to the analog pad is provided on a first side of the package facing in the first direction. In addition, a digital terminal which is connected to the digital pad is provided on a second side of the package facing in the second direction.
    Type: Application
    Filed: July 16, 2015
    Publication date: January 21, 2016
    Inventors: Hisahiro ITO, Shoichiro KASAHARA
  • Publication number: 20160020751
    Abstract: In order to achieve a circuit device capable of stably supplying an antenna with electric power in a broad power range to output a transmission signal, the circuit device includes a current source adapted to supply a first current in a first operation mode, and supply a second current higher than the first current in a second operation mode, and a drive section supplied with the electric power from the current source, and adapted to perform drive for outputting a transmission signal to an antenna via a matching circuit.
    Type: Application
    Filed: July 14, 2015
    Publication date: January 21, 2016
    Inventors: Minoru KOZAKI, Shoichiro KASAHARA
  • Patent number: 7805553
    Abstract: An integrated circuit device includes a common transceiver macrocell including a circuit necessary for host operation and a circuit necessary for device operation. The common transceiver macrocell includes an analog front-end circuit and a high-speed logic circuit. The high-speed logic circuit includes a parallel/serial conversion circuit, a first parallel interface which serves as an interface between an external circuit and the parallel/serial conversion circuit, a sampling clock generation circuit, a serial/parallel conversion circuit, and a second parallel interface which serves as an interface between the serial/parallel conversion circuit and the external circuit.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: September 28, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Shoichiro Kasahara, Fumikazu Komatsu, Mitsuaki Sawada, Yoshiyuki Kamihara, Takuya Ishida
  • Patent number: 7747807
    Abstract: A host controller includes a disconnection detection circuit 52 which compares a voltage level of a first differential signal DP of first and second differential signals DP and DM making up a differential signal pair corresponding to a given range in a frame packet with a comparison voltage CV, compares a voltage level of the second differential signal DM corresponding to a given range in the frame packet with the comparison voltage CV, and detects that a host and a device have been disconnected when the voltage level of at least one of the first and second differential signals DP and DM corresponding to the given range is higher than the comparison voltage CV.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: June 29, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Fumikazu Komatsu, Shoichiro Kasahara, Mitsuaki Sawada
  • Patent number: 7627845
    Abstract: A macrocell including a physical layer circuit includes a transmitter circuit and a receiver circuit connected with pads for differential signals DP and DM. The transmitter circuit includes a transmission driver which drives a signal line for the DP and a transmission driver which drives a signal line for the DM. When a direction from a side SD1 to a side SD3 of the macrocell is defined as a first direction, the transmission drivers are disposed on the side of the pads for the DP and DM in the first direction and are disposed line-symmetrically about a line SYL, and the receiver circuit is disposed on the side of the transmitter circuit in the first direction. A routing region of signal lines SLR1 and SLR2 for connecting the receiver circuit with the pads for the DP and DM is provided in the region between the transmission drivers.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: December 1, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Fumikazu Komatsu, Shoichiro Kasahara, Mitsuaki Sawada
  • Patent number: 7573298
    Abstract: A signal transmission circuit transmitting signals via first and second signal lines that provide a differential pair, includes: a current source installed between a first power source and a given node; a first switching element installed between the first signal line and the node; a second switching element installed between the second signal line and the node; a current control circuit varying a value of a current that flows from the constant current circuit, wherein the first and second signal lines are operated by the current from the constant current circuit via the first and second switching elements, the current being varied by the current control circuit.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: August 11, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Mitsuaki Sawada, Shoichiro Kasahara
  • Patent number: 7495474
    Abstract: An integrated circuit device includes a first transfer mode first transmitter circuit including first and second transmission drivers and a second transfer mode second transmitter circuit including third and fourth transmission drivers. A transistor PT1 of the first transmission driver and a transistor PT3 of the third transmission driver are formed in a P-type transistor area ARP1, a transistor NT1 of the first transmission driver and a transistor NT3 of the third transmission driver are formed in an N-type transistor area ARN1, a transistor PT2 of the second transmission driver and a transistor PT4 of the fourth transmission driver are formed in a P-type transistor area ARP2, and a transistor NT2 of the second transmission driver and a transistor NT4 of the fourth transmission driver are formed in an N-type transistor area ARN2.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: February 24, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Fumikazu Komatsu, Shoichiro Kasahara
  • Patent number: 7477615
    Abstract: A transceiver includes upstream differential signal lines DPUP and DMUP, downstream differential signal lines DPDW and DMDW, common differential signal lines DPCM and DMCM, a first transmission driver of which outputs are connected to DPUP and DMUP, a second transmission driver of which outputs are connected to DPDW and DMDW, a first switch circuit which connects the first transmission driver to a logic circuit during upstream connection and connects the second transmission driver to the logic circuit during downstream connection, a second switch circuit which respectively connects DPUP and DMUP to DPCM and DMCM during the upstream connection and respectively connects DPDW and DMDW to DPCM and DMCM during the downstream connection, and a third transmission driver connected to DPCM and DMCM.
    Type: Grant
    Filed: October 6, 2005
    Date of Patent: January 13, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Shun Oshita, Shoichiro Kasahara, Takuya Ishida, Yoshiyuki Kamihara
  • Patent number: 7474118
    Abstract: To provide a transmission circuit which can adequately perform a fast data transmission even to a receiving circuit of a host controller or a device controller with a low sensitivity. A transmission circuit transmitting a signal through first and second signal lines that form a differential pair and includes a first terminating resistor terminating the first signal line, a second terminating resistor terminating the second signal line and a terminating resistance control circuit generating a control signal for controlling terminating resistance values of the first terminating resistor and the second terminating resistor. A first resistor takes a first resistance value if a first control signal is active, a nth resistor takes a nth resistance value if a nth control signal is active, the first-nth resistors are coupled, one end of the coupled first-nth resistors is coupled to a reference potential and the other end is coupled to the first signal line or the second signal line.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: January 6, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Shoichiro Kasahara
  • Publication number: 20080155489
    Abstract: A macrocell including a physical layer circuit includes a transmitter circuit and a receiver circuit connected with pads for differential signals DP and DM. The transmitter circuit includes a transmission driver which drives a signal line for the DP and a transmission driver which drives a signal line for the DM. When a direction from a side SD1 to a side SD3 of the macrocell is defined as a first direction, the transmission drivers are disposed on the side of the pads for the DP and DM in the first direction and are disposed line-symmetrically about a line SYL, and the receiver circuit is disposed on the side of the transmitter circuit in the first direction. A routing region of signal lines SLR1 and SLR2 for connecting the receiver circuit with the pads for the DP and DM is provided in the region between the transmission drivers.
    Type: Application
    Filed: February 21, 2008
    Publication date: June 26, 2008
    Applicant: Seiko Epson Corporation
    Inventors: Fumikazu Komatsu, Shoichiro Kasahara, Mitsuaki Sawada
  • Patent number: 7383371
    Abstract: A physical layer circuit including: a VBUS detection circuit which makes a VBUS detection signal VBDET active when a VBUS voltage has exceeded a predetermined voltage; a receiver circuit which performs reception processing using signals DP and DM; and a reception control circuit which outputs an enable signal to the receiver circuit. When the signal VBDET is inactive, the reception control circuit makes the enable signals COMPENB, SEENB1 and SEENB2 inactive and disables the receiver circuit. When signals FCOMPENB, FSEENB1 and FSEENB2 set by a processing section are active but the signal VBDET is inactive, the reception control circuit makes the signals COMPENB, SEENB1 and SEENB2 inactive.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: June 3, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Shoichiro Kasahara
  • Patent number: 7360192
    Abstract: A macrocell including a physical layer circuit includes a transmitter circuit and a receiver circuit connected with pads for differential signals DP and DM. The transmitter circuit includes a transmission driver which drives a signal line for the DP and a transmission driver which drives a signal line for the DM. When a direction from a side SD1 to a side SD3 of the macrocell is defined as a first direction, the transmission drivers are disposed on the side of the pads for the DP and DM in the first direction and are disposed line-symmetrically about a line SYL, and the receiver circuit is disposed on the side of the transmitter circuit in the first direction. A routing region of signal lines SLR1 and SLR2 for connecting the receiver circuit with the pads for the DP and DM is provided in the region between the transmission drivers.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: April 15, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Fumikazu Komatsu, Shoichiro Kasahara, Mitsuaki Sawada
  • Publication number: 20070156932
    Abstract: An integrated circuit device includes a common transceiver macrocell including a circuit necessary for host operation and a circuit necessary for device operation. The common transceiver macrocell includes an analog front-end circuit and a high-speed logic circuit. The high-speed logic circuit includes a parallel/serial conversion circuit, a first parallel interface which serves as an interface between an external circuit and the parallel/serial conversion circuit, a sampling clock generation circuit, a serial/parallel conversion circuit, and a second parallel interface which serves as an interface between the serial/parallel conversion circuit and the external circuit.
    Type: Application
    Filed: November 22, 2006
    Publication date: July 5, 2007
    Inventors: Shoichiro Kasahara, Fumikazu Komatsu, Mitsuaki Sawada, Yoshiyuki Kamihara, Takuya Ishida
  • Publication number: 20070152705
    Abstract: To provide a transmission circuit which can adequately perform a fast data transmission even to a receiving circuit of a host controller or a device controller with a low sensitivity. A transmission circuit transmitting a signal through first and second signal lines that form a differential pair and includes a first terminating resistor terminating the first signal line, a second terminating resistor terminating the second signal line and a terminating resistance control circuit generating a control signal for controlling terminating resistance values of the first terminating resistor and the second terminating resistor. A first resistor takes a first resistance value if a first control signal is active, a nth resistor takes a nth resistance value if a nth control signal is active, the first-nth resistors are coupled, one end of the coupled first-nth resistors is coupled to a reference potential and the other end is coupled to the first signal line or the second signal line.
    Type: Application
    Filed: March 14, 2007
    Publication date: July 5, 2007
    Applicant: Seiko Epson Corporation
    Inventor: Shoichiro Kasahara
  • Publication number: 20070121264
    Abstract: A signal transmission circuit transmitting signals via a first and a second signal lines that provide a differential pair, includes: a current source installed between a first power source and a given node; a first switching element installed between the first signal line and the node; a second switching element installed between the second signal line and the node; a current control circuit varying a value of a current that flows from the constant current circuit, wherein the first and second signal lines are operated by the current from the constant current circuit via the first and second switching elements, the current being varied by the current control circuit.
    Type: Application
    Filed: November 21, 2006
    Publication date: May 31, 2007
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Mitsuaki SAWADA, Shoichiro KASAHARA
  • Publication number: 20070120579
    Abstract: An integrated circuit device includes a first transfer mode first transmitter circuit including first and second transmission drivers and a second transfer mode second transmitter circuit including third and fourth transmission drivers. A transistor PT1 of the first transmission driver and a transistor PT3 of the third transmission driver are formed in a P-type transistor area ARP1, a transistor NT1 of the first transmission driver and a transistor NT3 of the third transmission driver are formed in an N-type transistor area ARN1, a transistor PT2 of the second transmission driver and a transistor PT4 of the fourth transmission driver are formed in a P-type transistor area ARP2, and a transistor NT2 of the second transmission driver and a transistor NT4 of the fourth transmission driver are formed in an N-type transistor area ARN2.
    Type: Application
    Filed: November 22, 2006
    Publication date: May 31, 2007
    Inventors: Fumikazu Komatsu, Shoichiro Kasahara