Abstract: There are provided a transmission circuit capable of stabilizing high-speed data transfer by driving current, a data transfer control device, and electronic equipment. An HS current driver (transmission circuit) included in a data transfer control device has a current source connected between a first power supply AVDD and a node ND, and switching devices SW1 to SW3, one ends of which are connected to the node ND. The other end of the switching device SW1 is connected to a DP terminal. The other end of the switching device SW2 is connected to a DM terminal. The other end of the switching device SW3 is connected to a DA terminal. The DA terminal is connected to a second power supply AVSS inside or outside the transmission circuit. The transmission circuit is configured so that impedances of each current path from the node ND through the switching devices SW1 to SW3 become substantially equal when the switching device is turned on.

Abstract: There are provided a semiconductor integrated device capable of achieving stable high-speed data transfer through a differential pair of signal lines and electronic equipment including the semiconductor integrated device. In a signal-transmission period in which current is driven through one of first and second signal lines forming a differential pair, current from a constant current source is caused to flow through a current path to one of a DP pad and DM pad. Current is caused to flow into a DA pad in a period other than the signal-transmission period. A layout arrangement of the current paths from a node ND to which current from the constant current source is supplied to the DP pad and the DM pad is symmetrical. The DA pad is disposed between the DP pad and the DM pad.

Abstract: A macrocell MC1 including a physical-layer circuit in accordance with USB 2.0 or the like is placed at a corner of an integrated circuit device ICD. Data terminals DP and DM are placed in an I/O region IOR1 along a side SD1; and power terminals PVDD, PVSS, XVDD, and XVSS and clock terminals XI and XO of a clock generation circuit and a sampling clock circuit are placed in an I/O region IOR2 along a side SD2. An interface region and a macrocell MC2 including user-specified logic are provided along a side SD3. A reception circuit is placed on a DR1 side of IOR1, a clock generation circuit is placed on a DR2 side of IOR2, and a sampling clock generation circuit is placed on the DR1 side of the reception circuit and also the DR2 side of the clock generation circuit. A transmission circuit is placed on the DR2 side of the reception circuit and on the DR1 side of the data terminals DP and DM.

Abstract: There are provided a transmission circuit capable of stabilizing high-speed data transfer by driving current, a data transfer control device, and electronic equipment. An HS current driver (transmission circuit) included in a data transfer control device has a current source connected between a first power supply AVDD and a node ND, and switching devices SW1 to SW3, one ends of which are connected to the node ND. The other end of the switching device SW1 is connected to a DP terminal. The other end of the switching device SW2 is connected to a DM terminal. The other end of the switching device SW3 is connected to a DA terminal. The DA terminal is connected to a second power supply AVSS inside or outside the transmission circuit. The transmission circuit is configured so that impedances of each current path from the node ND through the switching devices SW1 to SW3 become substantially equal when the switching device is turned on.

Abstract: A clock generation circuit capable of generating a high-frequency clock with a simple circuit configuration, together with a data transfer control device and an electronic instrument using the same. The clock generation circuit has: serially-connected inversion circuits IV0 to IV4 in which an output of IV4 is connected to an input of IV0 by a feedback line FL; and buffer circuits BF0 to BF4 which receives outputs from IV0 to IV4. The inversion circuits IV0 to IV4 are disposed along a line LN1 and the buffer circuits BF0 to BF4 are disposed along a line LN2 that is parallel to the feedback line FL but different from LN1. Dummy lines DL0 to DL3 each of which having parasitic capacitance that is equal to that of the feedback line FL are connected to the inversion circuits IV0 to IV3, to equalize the phase differences between clocks CK0 to CK4. The feedback line FL and the dummy lines DL0 to DL3 are disposed in a region between the inversion circuits IV0 to IV4 and the buffer circuits BF0 to BF4.

Abstract: A constant-current generating circuit for implementing high-precision analog output is disclosed in an image processing apparatus that includes a digital-to-analog conversion circuit (DAC) for converting a digital data image signal into analog data. For stably generating a constant current, current-generating transistors formed of basic-capacitance transistors are regularly disposed in the form of a SEA OF GATES (SOG). With this arrangement, uniform pattern formation based on the basic-capacitance transistors can be achieved, so that all the factors of the constant-current generating circuit, such as the drain resistance, the source resistance, etc., can be made uniform, thereby stably generating a constant current. The whole constant-current generating circuit group forming the digital-to-analog conversion circuit becomes totally independent due to the above-described arrangement, thereby stabilizing a constant current within one channel.

Abstract: The present invention provides a reset circuit with two different threshold input voltages. The reset circuit of the present invention is located within a processor, and is designed to control the reset functions of both the processor and the chips located peripheral to the processor. The reset circuit includes a first buffer with a first threshold voltage level. The input of the first buffer is connected to a reset signal and the output of the first buffer is connected to control the reset function of at least one chip that is peripheral to the processor. A second buffer is provided with a second threshold voltage level that is higher than the first threshold voltage level. The input of the second buffer is connected to the reset signal and the output of the second buffer is connected to control the reset function of the processor. The reset circuit guarantees that the processor is reset after the peripheral chips subsequent to power up.