Abstract: A signal transmission circuit transmitting signals via first and second signal lines that provide a differential pair, includes: a current source installed between a first power source and a given node; a first switching element installed between the first signal line and the node; a second switching element installed between the second signal line and the node; a current control circuit varying a value of a current that flows from the constant current circuit, wherein the first and second signal lines are operated by the current from the constant current circuit via the first and second switching elements, the current being varied by the current control circuit.

Abstract: An integrated circuit device includes a first transfer mode first transmitter circuit including first and second transmission drivers and a second transfer mode second transmitter circuit including third and fourth transmission drivers. A transistor PT1 of the first transmission driver and a transistor PT3 of the third transmission driver are formed in a P-type transistor area ARP1, a transistor NT1 of the first transmission driver and a transistor NT3 of the third transmission driver are formed in an N-type transistor area ARN1, a transistor PT2 of the second transmission driver and a transistor PT4 of the fourth transmission driver are formed in a P-type transistor area ARP2, and a transistor NT2 of the second transmission driver and a transistor NT4 of the fourth transmission driver are formed in an N-type transistor area ARN2.

Abstract: A transceiver includes upstream differential signal lines DPUP and DMUP, downstream differential signal lines DPDW and DMDW, common differential signal lines DPCM and DMCM, a first transmission driver of which outputs are connected to DPUP and DMUP, a second transmission driver of which outputs are connected to DPDW and DMDW, a first switch circuit which connects the first transmission driver to a logic circuit during upstream connection and connects the second transmission driver to the logic circuit during downstream connection, a second switch circuit which respectively connects DPUP and DMUP to DPCM and DMCM during the upstream connection and respectively connects DPDW and DMDW to DPCM and DMCM during the downstream connection, and a third transmission driver connected to DPCM and DMCM.

Abstract: To provide a transmission circuit which can adequately perform a fast data transmission even to a receiving circuit of a host controller or a device controller with a low sensitivity. A transmission circuit transmitting a signal through first and second signal lines that form a differential pair and includes a first terminating resistor terminating the first signal line, a second terminating resistor terminating the second signal line and a terminating resistance control circuit generating a control signal for controlling terminating resistance values of the first terminating resistor and the second terminating resistor. A first resistor takes a first resistance value if a first control signal is active, a nth resistor takes a nth resistance value if a nth control signal is active, the first-nth resistors are coupled, one end of the coupled first-nth resistors is coupled to a reference potential and the other end is coupled to the first signal line or the second signal line.

Abstract: A macrocell including a physical layer circuit includes a transmitter circuit and a receiver circuit connected with pads for differential signals DP and DM. The transmitter circuit includes a transmission driver which drives a signal line for the DP and a transmission driver which drives a signal line for the DM. When a direction from a side SD1 to a side SD3 of the macrocell is defined as a first direction, the transmission drivers are disposed on the side of the pads for the DP and DM in the first direction and are disposed line-symmetrically about a line SYL, and the receiver circuit is disposed on the side of the transmitter circuit in the first direction. A routing region of signal lines SLR1 and SLR2 for connecting the receiver circuit with the pads for the DP and DM is provided in the region between the transmission drivers.

Abstract: A physical layer circuit including: a VBUS detection circuit which makes a VBUS detection signal VBDET active when a VBUS voltage has exceeded a predetermined voltage; a receiver circuit which performs reception processing using signals DP and DM; and a reception control circuit which outputs an enable signal to the receiver circuit. When the signal VBDET is inactive, the reception control circuit makes the enable signals COMPENB, SEENB1 and SEENB2 inactive and disables the receiver circuit. When signals FCOMPENB, FSEENB1 and FSEENB2 set by a processing section are active but the signal VBDET is inactive, the reception control circuit makes the signals COMPENB, SEENB1 and SEENB2 inactive.

Abstract: A macrocell including a physical layer circuit includes a transmitter circuit and a receiver circuit connected with pads for differential signals DP and DM. The transmitter circuit includes a transmission driver which drives a signal line for the DP and a transmission driver which drives a signal line for the DM. When a direction from a side SD1 to a side SD3 of the macrocell is defined as a first direction, the transmission drivers are disposed on the side of the pads for the DP and DM in the first direction and are disposed line-symmetrically about a line SYL, and the receiver circuit is disposed on the side of the transmitter circuit in the first direction. A routing region of signal lines SLR1 and SLR2 for connecting the receiver circuit with the pads for the DP and DM is provided in the region between the transmission drivers.

Abstract: To provide a transmission circuit which can adequately perform a fast data transmission even to a receiving circuit of a host controller or a device controller with a low sensitivity. A transmission circuit transmitting a signal through first and second signal lines that form a differential pair and includes a first terminating resistor terminating the first signal line, a second terminating resistor terminating the second signal line and a terminating resistance control circuit generating a control signal for controlling terminating resistance values of the first terminating resistor and the second terminating resistor. A first resistor takes a first resistance value if a first control signal is active, a nth resistor takes a nth resistance value if a nth control signal is active, the first-nth resistors are coupled, one end of the coupled first-nth resistors is coupled to a reference potential and the other end is coupled to the first signal line or the second signal line.

Abstract: An integrated circuit device includes a common transceiver macrocell including a circuit necessary for host operation and a circuit necessary for device operation. The common transceiver macrocell includes an analog front-end circuit and a high-speed logic circuit. The high-speed logic circuit includes a parallel/serial conversion circuit, a first parallel interface which serves as an interface between an external circuit and the parallel/serial conversion circuit, a sampling clock generation circuit, a serial/parallel conversion circuit, and a second parallel interface which serves as an interface between the serial/parallel conversion circuit and the external circuit.

Abstract: A signal transmission circuit transmitting signals via a first and a second signal lines that provide a differential pair, includes: a current source installed between a first power source and a given node; a first switching element installed between the first signal line and the node; a second switching element installed between the second signal line and the node; a current control circuit varying a value of a current that flows from the constant current circuit, wherein the first and second signal lines are operated by the current from the constant current circuit via the first and second switching elements, the current being varied by the current control circuit.

Abstract: An integrated circuit device includes a first transfer mode first transmitter circuit including first and second transmission drivers and a second transfer mode second transmitter circuit including third and fourth transmission drivers. A transistor PT1 of the first transmission driver and a transistor PT3 of the third transmission driver are formed in a P-type transistor area ARP1, a transistor NT1 of the first transmission driver and a transistor NT3 of the third transmission driver are formed in an N-type transistor area ARN1, a transistor PT2 of the second transmission driver and a transistor PT4 of the fourth transmission driver are formed in a P-type transistor area ARP2, and a transistor NT2 of the second transmission driver and a transistor NT4 of the fourth transmission driver are formed in an N-type transistor area ARN2.

Abstract: To provide a transmission circuit which can adequately perform a fast data transmission even to a receiving circuit of a host controller or a device controller with a low sensitivity. A transmission circuit transmitting a signal through first and second signal lines that form a differential pair and includes a first terminating resistor terminating the first signal line, a second terminating resistor terminating the second signal line and a terminating resistance control circuit generating a control signal for controlling terminating resistance values of the first terminating resistor and the second terminating resistor. A first resistor takes a first resistance value if a first control signal is active, a nth resistor takes a nth resistance value if a nth control signal is active, the first-nth resistors are coupled, one end of the coupled first-nth resistors is coupled to a reference potential and the other end is coupled to the first signal line or the second signal line.

Abstract: A host controller includes a disconnection detection circuit 52 which compares a voltage level of a first differential signal DP of first and second differential signals DP and DM making up a differential signal pair corresponding to a given range in a frame packet with a comparison voltage CV, compares a voltage level of the second differential signal DM corresponding to a given range in the frame packet with the comparison voltage CV, and detects that a host and a device have been disconnected when the voltage level of at least one of the first and second differential signals DP and DM corresponding to the given range is higher than the comparison voltage CV.

Abstract: A transceiver includes upstream differential signal lines DPUP and DMUP, downstream differential signal lines DPDW and DMDW, common differential signal lines DPCM and DMCM, a first transmission driver of which outputs are connected to DPUP and DMUP, a second transmission driver of which outputs are connected to DPDW and DMDW, a first switch circuit which connects the first transmission driver to a logic circuit during upstream connection and connects the second transmission driver to the logic circuit during downstream connection, a second switch circuit which respectively connects DPUP and DMUP to DPCM and DMCM during the upstream connection and respectively connects DPDW and DMDW to DPCM and DMCM during the downstream connection, and a third transmission driver connected to DPCM and DMCM.

Abstract: A clock generation circuit capable of generating a high-frequency clock with a simple circuit configuration, together with a data transfer control device and an electronic instrument using the same. The clock generation circuit has: serially-connected inversion circuits IV0 to IV4 in which an output of IV4 is connected to an input of IV0 by a feedback line FL; and buffer circuits BF0 to BF4 which receives outputs from IV0 to IV4. The inversion circuits IV0 to IV4 are disposed along a line LN1 and the buffer circuits BF0 to BF4 are disposed along a line LN2 that is parallel to the feedback line FL but different from LN1. Dummy lines DL0 to DL3 each of which having parasitic capacitance that is equal to that of the feedback line FL are connected to the inversion circuits IV0 to IV3, to equalize the phase differences between clocks CK0 to CK4. The feedback line FL and the dummy lines DL0 to DL3 are disposed in a region between the inversion circuits IV0 to IV4 and the buffer circuits BF0 to BF4.

Abstract: To provide a transmission circuit which can adequately perform a fast data transmission even to a receiving circuit of a host controller or a device controller with a low sensitivity. A transmission circuit transmitting a signal through first and second signal lines that form a differential pair and includes a first terminating resistor terminating the first signal line, a second terminating resistor terminating the second signal line and a terminating resistance control circuit generating a control signal for controlling terminating resistance values of the first terminating resistor and the second terminating resistor. A first resistor takes a first resistance value if a first control signal is active, a nth resistor takes a nth resistance value if a nth control signal is active, the first-nth resistors are coupled, one end of the coupled first-nth resistors is coupled to a reference potential and the other end is coupled to the first signal line or the second signal line.

Abstract: A macrocell including a physical layer circuit includes a transmitter circuit and a receiver circuit connected with pads for differential signals DP and DM. The transmitter circuit includes a transmission driver which drives a signal line for the DP and a transmission driver which drives a signal line for the DM. When a direction from a side SD1 to a side SD3 of the macrocell is defined as a first direction, the transmission drivers are disposed on the side of the pads for the DP and DM in the first direction and are disposed line-symmetrically about a line SYL, and the receiver circuit is disposed on the side of the transmitter circuit in the first direction. A routing region of signal lines SLR1 and SLR2 for connecting the receiver circuit with the pads for the DP and DM is provided in the region between the transmission drivers.

Abstract: A physical layer circuit including: a VBUS detection circuit which makes a VBUS detection signal VBDET active when a VBUS voltage has exceeded a predetermined voltage; a receiver circuit which performs reception processing using signals DP and DM; and a reception control circuit which outputs an enable signal to the receiver circuit. When the signal VBDET is inactive, the reception control circuit makes the enable signals COMPENB, SEENB1 and SEENB2 inactive and disables the receiver circuit. When signals FCOMPENB, FSEENB1 and FSEENB2 set by a processing section are active but the signal VBDET is inactive, the reception control circuit makes the signals COMPENB, SEENB1 and SEENB2 inactive.

Abstract: There are provided a semiconductor integrated device capable of achieving stable high-speed data transfer through a differential pair of signal lines and electronic equipment including the semiconductor integrated device. In a signal-transmission period in which current is driven through one of first and second signal lines forming a differential pair, current from a constant current source is caused to flow through a current path to one of a DP pad and DM pad. Current is caused to flow into a DA pad in a period other than the signal-transmission period. A layout arrangement of the current paths from a node ND to which current from the constant current source is supplied to the DP pad and the DM pad is symmetrical. The DA pad is disposed between the DP pad and the DM pad.

Abstract: A macrocell MC1 including a physical-layer circuit in accordance with USB 2.0 or the like is placed at a corner of an integrated circuit device ICD. Data terminals DP and DM are placed in an I/O region IOR1 along a side SD1; and power terminals PVDD, PVSS, XVDD, and XVSS and clock terminals XI and XO of a clock generation circuit and a sampling clock circuit are placed in an I/O region IOR2 along a side SD2. An interface region and a macrocell MC2 including user-specified logic are provided along a side SD3. A reception circuit is placed on a DR1 side of IOR1, a clock generation circuit is placed on a DR2 side of IOR2, and a sampling clock generation circuit is placed on the DR1 side of the reception circuit and also the DR2 side of the clock generation circuit. A transmission circuit is placed on the DR2 side of the reception circuit and on the DR1 side of the data terminals DP and DM.