Abstract: The present disclosure relates generally to an interface between a host processor device and a peripheral device, such as a camera or sensor, and, more particularly, to improving the generation of data signals with embedded clock information to be more rate-flexible and power efficient. Improved techniques are described herein to embed a clock signal into a data signal (e.g., to minimize the number of channels needed)—while allowing for a variable link rate and avoiding the need for a phase lock loop (PLL) and/or long link training times at the receiver, which can consume large amounts of power and on-chip area. In some embodiments, a modified Manchester encoding scheme, e.g., using a fixed delay for its mid-bit transitions (and wherein the delay is independent of link rate), is used to achieve the dual aims of rate flexibility and power efficiency for an improved data signal interface with embedded clock information.

Abstract: Disclosed herein are systems, methods, and devices for sensor systems, in which one or more sensors are linked with a host processor. The sensors may transmit a sequence of frames, such as video frames to the host processor. The methods may include determining and/or adjusting a period or frequency of a first clock or oscillator in a sensor device, based on two signals applied by the sensor to a sequence of frames. The host processor may use its own clock or oscillator to determine an elapsed time between the two signals to determine the period or frequency of the first clock and may apply an adjustment to the sensor's clock. Other embodiments are directed to sensor systems in which two or more sensors may transmit respective sequences of frames to the host processor. The methods may provide the host processor a means to synchronize transmission of the frames from the sensors. The systems, methods, and devices may avoid the need for dedicated timing or synchronization lines.

Abstract: Methods and apparatus for converting streaming media between different formats. A bridging device for e.g., Camera Serial Interface (CSI) and DisplayPort is disclosed. Both the CSI and DisplayPort technologies use low power mode operation during blanking intervals of a video transmission. However, the CSI interface can wake up in a very short amount of time (e.g., ˜400 ns), but the DisplayPort interface takes significantly longer to perform link training (e.g., ˜1 ms). Various embodiments of the present disclosure use frame signaling trigger to start a wait time interval timer; the wait time interval can be used by the bridge device to wake up the DisplayPort interface ahead of the CSI2 D-PHY interface, thereby ensuring that both links are active at the same time. This “wake-up” technique can greatly reduce the size of buffering memories that are required.

Abstract: Methods and apparatus for converting streaming media between different formats. A bridging device for e.g., Camera Serial Interface (CSI) and DisplayPort is disclosed. Both the CSI and DisplayPort technologies use low power mode operation during blanking intervals of a video transmission. However, the CSI interface can wake up in a very short amount of time (e.g., ˜400 ns), but the DisplayPort interface takes significantly longer to perform link training (e.g., ˜1 ms). Various embodiments of the present disclosure use frame signaling trigger to start a wait time interval timer; the wait time interval can be used by the bridge device to wake up the DisplayPort interface ahead of the CSI2 D-PHY interface, thereby ensuring that both links are active at the same time. This “wake-up” technique can greatly reduce the size of buffering memories that are required.

Abstract: A method and an apparatus are provided. The apparatus may include a clock recovery circuit having a plurality of input latches configured to assume a first state when a first pulse is received in one or more of a plurality of input signals, combinational logic configured to provide a second pulse response to the first pulse, a delay circuit configured to produce a third pulse on a receive clock that is delayed with respect to the second pulse, a plurality of output flip-flops configured to capture the first state when triggered by the third pulse. The first state may identify which of the plurality of input signals received input pulses.

Abstract: To accommodate multiple masters over bus architectures supporting a single master device, a mechanism is provided for an inactive master device to assert an in-band IRQ. A current master then polls the other inactive master devices over a shared data bus to ascertain which inactive master device is asserting the IRQ. Upon identifying the asserting inactive master device, the current master device grants control of the data bus to the new master device, thereby making the inactive master the new active master device.

Abstract: A method and an apparatus are provided. The apparatus may include a clock recovery circuit having a plurality of input latches configured to assume a first state when a first pulse is received in one or more of a plurality of input signals, combinational logic configured to provide a second pulse response to the first pulse, a delay circuit configured to produce a third pulse on a receive clock that is delayed with respect to the second pulse, a plurality of output flip-flops configured to capture the first state when triggered by the third pulse. The first state may identify which of the plurality of input signals received input pulses.

Abstract: A method and an apparatus are provided. The apparatus may include a clock recovery circuit having a plurality of input latches configured to assume a first state when a first pulse is received in one or more of a plurality of input signals, combinational logic configured to provide a second pulse response to the first pulse, a delay circuit configured to produce a third pulse on a receive clock that is delayed with respect to the second pulse, a plurality of output flip-flops configured to capture the first state when triggered by the third pulse. The first state may identify which of the plurality of input signals received input pulses.

Abstract: A first set of devices is coupled to a first bus, a second bus, and configured to communicate over the first bus according to a first communication protocol. A second set of devices is also coupled to the first bus and configured to communicate over the first bus according to both the first communication protocol and a second communication protocol. In a first mode, the first set of devices and second set of devices may concurrently communicate over the first bus using the first communication protocol. In a second mode, the second set of devices communicate using the second communication protocol over the bus, and the first set of devices to stop operating on the first bus. An enable command is sent by at least one of the second set of devices over a second bus to cause the first set of devices to resume activity over the first bus.

Abstract: Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. A method for transmitting data on the multi-wire interface includes transmitting data on a multi-wire interface includes obtaining a plurality of bits to be transmitted over a plurality of connectors, converting the plurality of bits into a sequence of symbols, and transmitting the sequence of symbols on the plurality of connectors. A predetermined number of least significant bits in the plurality of bits may be used for error detection. The predetermined number of least significant bits may have a constant value that is different from each of a plurality of error values. A symbol error affecting one or two symbols in the sequence of symbols may cause a decoded version of the predetermined number of least significant bits to have value that is one of a plurality of error values.

Abstract: Methods, apparatus, and computer program products are described, which provide a mechanism that enables data to be written into registers of a slave device without a free-running clock, while facilitating an efficient sleep and wakeup mechanism for slave devices. A receiver device may receive a plurality of symbols over a shared bus, extract a receive clock signal embedded in symbol-to-symbol transitions of the plurality of symbols, convert the plurality of symbols into a transition number, convert the transition number into data bits, and store at least a portion of the data bits into one or more registers using only the receive clock signal. The receiver device may start a down counter upon detection of a first cycle of the clock signal, trigger a marker when the down counter reaches a pre-defined value, and use the marker to store at least a portion of the data bits into registers.

Abstract: System, methods and apparatus are described that offer improved performance of an Inter-Integrated Circuit (I2C) bus. Primary data may be encoded in first signaling in accordance with I2C bus protocols, and the first signaling may be combined with second signaling to obtain combined signaling for transmission on an I2C bus. Secondary data may be encoded in the second signaling with the combined signaling remaining compatible with the I2C bus protocols. The second signaling may modulate a voltage level of at least one signal in the first signaling. The second signaling may pulse-width modulate a clock signal transmitted on the I2C bus. The second signaling may modify a start condition between bytes transmitted on the I2C bus. The second signaling may add a plurality of short pulses to a clock signal transmitted in the first signaling.

Abstract: A method for enabling 8-bit data word access over a protocol limited to 16-bit data word access is provided. Data may be encapsulated within the lowest 19 bits of a 20-bit number. If it is ascertained that an 8-bit data word is to be used in a system supporting only 16-bit data word access, a byte-enable indicator may be provided within a most significant bit of the 20-bit number while also allocating an 8-bit data region for transfer of the 8-bit data word. The 20-bit number may then be transcoded into a 12-digit ternary number, wherein a residual numerical region is defined as a number space by which a first numerical region defined for the 12-digit ternary number exceeds a second numerical region defined by the lowest 19 bits of the 20-bit number.

Abstract: In a shared bus where communications are managed by a master device, direct slave device to slave device (S2S) communications is implemented. A first slave device wanting to communicate with a second slave device may make a S2S communication request to the master device. The request may include a requested number of words that the first slave device wishes to send over the shared bus. The master device may have a current word limit which may vary based upon operating parameters. The master device may deny the request if the requested number of words is greater than the current word limit or if it does not support S2S communications. Denial of the request may also be for other reasons, like activity over the shared bus. If the master device grants the request, the slave device may send the requested number of words to another slave device over the shared bus.

Abstract: System, methods and apparatus are described that offer improved performance of an Inter-Integrated Circuit (I2C) bus. Primary data may be encoded in first signaling in accordance with I2C bus protocols, and the first signaling may be combined with second signaling to obtain combined signaling for transmission on an I2C bus. Secondary data may be encoded in the second signaling with the combined signaling remaining compatible with the I2C bus protocols. The second signaling may modulate a voltage level of at least one signal in the first signaling. The second signaling may pulse-width modulate a clock signal transmitted on the I2C bus. The second signaling may modify a start condition between bytes transmitted on the I2C bus. The second signaling may add a plurality of short pulses to a clock signal transmitted in the first signaling.

Abstract: A master device is provided which is coupled to a shared single line interrupt request (IRQ) bus and a control data bus. The master device group slave devices coupled to the shared single line IRQ bus into one or more groups, where each group is associated with a different IRQ signal. The master device then monitors the IRQ bus to ascertain when an IRQ signal is asserted by at least one slave device. The master device then identifies a group to with which the IRQ signal is associated. The slave devices for the identified group are then scanned or queried by the master device to ascertain which slave device asserted the IRQ signal on the IRQ bus. Each group uses a distinguishable IRQ signal to allow the master device to ascertain which group to query or scan.

Abstract: Apparatus, systems and methods for improving coexistence on a multi-wire interface are disclosed. A method of transmitting data on a multi-wire interface includes providing a plurality of data bits in a word to be transmitted on the multi-wire interface, transcoding the word to be transmitted to obtain a first multi-digit ternary number representative of the numerical value of the word to be transmitted, inserting marker digits into the first multi-digit ternary number to obtain a second multi-digit ternary number, and generating a sequence of symbols. Each symbol in the sequence of symbols may be generated using a digit of the second multi-digit ternary number and a preceding symbol in the sequence of symbols. The preconfigured values and the preconfigured locations of the marker digits may be selected to prevent occurrence of I3C HDR Exit or HDR I3C Restart signaling when the sequence of symbols is transmitted on the multi-wire interface.

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A method performed by a slave device coupled to a serial bus includes detecting an event related to a function of the slave device, initiating a first counter in the slave device, asserting an in-band interrupt request by driving at least one signal on the serial bus, and transmitting content of the first counter to a bus master coupled to the serial bus during an interrupt handling procedure. The first counter may count cycles of a clock used by the slave device or occurrences of a signaling state or condition on the serial bus. The content of the first counter may be used to determine a time stamp for the event.

Abstract: Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. One such method includes providing a plurality of data bits in a word to be transmitted such that a bit-order of the plurality of data bits is flipped with respect to hit-order of the word to be transmitted, providing an EDC as one or more least significant bits of the word to be transmitted and adjacent to a most significant bit of the plurality of data bits in the word to be transmitted, converting the word to be transmitted into a transition number, and transmitting the transition number as a sequence of symbols on the multi-wire interface. The EDC may have a length and a known, fixed value, and length selected to enable a decoder to detect or correct one or more symbol errors in the sequence of symbols.

Abstract: In a shared bus where communications are managed by a master device, direct slave device to slave device (S2S) communications is implemented. A first slave device wanting to communicate with a second slave device may make a S2S communication request to the master device. The request may include a requested number of words that the first slave device wishes to send over the shared bus. The master device may have a current word limit which may vary based upon operating parameters. The master device may deny the request if the requested number of words is greater than the current word limit or if it does not support S2S communications. Denial of the request may also be for other reasons, like activity over the shared bus. If the master device grants the request, the slave device may send the requested number of words to another slave device over the shared bus.