Abstract: A clock recovery circuit is provided comprising a receiver circuit and a clock extraction circuit. The receiver circuit may be adapted to decode a differentially encoded signal on a plurality of data lines, where at least one data symbol is differentially encoded in state transitions of the differentially encoded signal. The clock extraction circuit may be adapted to obtain a clock signal from state transition signals derived from the state transitions.

Abstract: Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. A method for transmitting data on the multi-wire interface includes transmitting data on a multi-wire interface includes obtaining a plurality of bits to be transmitted over a plurality of connectors, converting the plurality of bits into a sequence of symbols, and transmitting the sequence of symbols on the plurality of connectors. A predetermined number of least significant bits in the plurality of bits may be used for error detection. The predetermined number of least significant bits may have a constant value that is different from each of a plurality of error values. A symbol error affecting one or two symbols in the sequence of symbols may cause a decoded version of the predetermined number of least significant bits to have value that is one of a plurality of error values.

Abstract: Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. A method for correcting transmission errors in multi-wire transition-encoded interface may include determining whether a symbol error is present in the sequence of symbols based on a value of an error detection code (EDC) in the received plurality of bits, generating one or more permutations of the sequence of symbols, where each permutation includes one symbol that is different from corresponding symbols in the sequence of symbols and different from corresponding symbols in other permutations. A permutation in the one or more permutations may be identified as including a corrected sequence of symbols when it produces a decoded EDC value that matches an expected EDC value. The expected EDC value may correspond to a predefined value for EDCs transmitted over the multi-wire interface to enable detection of up to two symbol errors at the receiver.

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A method performed by a slave device coupled to a serial bus includes detecting an event related to a function of the slave device, initiating a first counter in the slave device, asserting an in-band interrupt request by driving at least one signal on the serial bus, and transmitting content of the first counter to a bus master coupled to the serial bus during an interrupt handling procedure. The first counter may count cycles of a clock used by the slave device or occurrences of a signaling state or condition on the serial bus. The content of the first counter may be used to determine a time stamp for the event.

Abstract: A method and an apparatus are provided. The apparatus may includes a clock recovery circuit having a comparator that provides a comparison signal indicating whether an input signal matches a level-latched instance of the input signal, a first set-reset latch that provides a filtered version of the comparison signal, where the first set-reset latch is set by a first-occurring active transition of the comparison signal and is unaffected by further transitions of the comparison signal that occur during a predefined period of time, delay circuitry that receives the filtered version of the comparison signal and outputs a first pulse on a first clock signal, and a second set-reset latch configured to provide a second pulse on an output clock signal when the first pulse is present on the first clock signal and the comparison signal indicates that the level-latched instance of the input signal does not match the input signal.

Abstract: A method for performing multi-wire signaling encoding is provided in which a clock signal is encoded within symbol transitions. A sequence of data bits is converted into a plurality of m transition numbers. Each transition number is converted into a sequential symbol number from a set of sequential symbol numbers. The sequential symbol number is converted into a raw symbol that can be transmitted over a plurality of differential drivers. The raw symbol is transmitted spread over a plurality of n wires, wherein the clock signal is effectively embedded in the transmission of raw symbols since the conversion from transition number into a sequential symbol number guarantees that no two consecutive raw symbols are the same. The raw symbol is guaranteed to have a non-zero differential voltage across all pairs of the plurality of n wires.

Abstract: A method for performing multi-wire signaling encoding is provided in which a clock signal is encoded within symbol transitions. A sequence of data bits is converted into a plurality of m transition numbers. Each transition number is converted into a sequential number from a set of sequential numbers. The sequential number is converted into a raw symbol that can be transmitted over a plurality of differential drivers. The raw symbol is transmitted spread over a plurality of n wires, wherein the clock signal is effectively embedded in the transmission of raw symbols since the conversion from transition number into a sequential number guarantees that no two consecutive raw symbols are the same. The raw symbol is guaranteed to have a non-zero differential voltage across all pairs of the plurality of n wires.

Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A data payload may be converted to a set of transition numbers, the transition numbers may be converted to a sequence of symbols and an error correction code (ECC) may be calculated from symbols in the sequence of symbols. The ECC corresponds to the data payload and the ECC may be appended to the data payload such that the set of transition numbers includes transition numbers corresponding to the ECC. The sequence of symbols is then transmitted on a plurality of signal wires. Clock information is encoded in the sequence of symbols. The clock information may be encoded by ensuring that each pair of consecutive symbols in the sequence of symbols includes two symbols that produce different signaling states on the plurality of signal wires.

Abstract: A plurality of line interfaces is configured to receive a spread signal over the plurality of line interface. The spread signal carrying symbols with guaranteed symbol-to-symbol state transitions between consecutive symbols. The spread signal is defined by a plurality of transition signals including a first signal over a first line interface. A clock signal is extracted based on a comparison between a first instance of the first signal and a delayed second instance of the first signal. The delayed second instance of the first signal is sampled based on the clock signal to provide a symbol output. The clock extraction circuit is further adapted to generate the clock signal based on additional comparisons between a first instance of a second signal, within the plurality of transition signals, and a delayed second instance of the second signal, where the first and second signals are concurrent signals received over different line interfaces.

Abstract: Methods and systems are disclosed for damping unwanted vibrations or ringing of a lens in an imaging device. For example, one method includes determining a target distance to move a lens, and dividing the target distance into multiple steps having at least a first step and a subsequent step, moving the lens, via an actuator, by the first step, thereby causing a first vibration, retrieving a damping parameter indicative of a time delay, the damping parameter being based on at least one characteristic of the actuator and the number of steps, and repeating said moving the lens at least one subsequent step after delaying the subsequent step by one of the damping parameters, each moving the lens a subsequent step causing a subsequent vibration, and the damping parameters affecting the vibration such that the first and subsequent vibrations at least in part modify each other to lower overall vibration.

Abstract: Methods and systems are disclosed for determining at least one actuation characteristic of an imaging device. For example, one method includes determining a target distance to move a lens by an actuator to focus a scene on an image sensor, where moving the lens by the actuator causes an associated lens vibration having at least one actuation characteristic, determining a scan sequence having a plurality of successive measurements, each measurement having at least a first measurement parameter and subsequent measurement parameter, each measurement parameter including at least one step and at least one time delay, moving the lens the target distance for each successive measurement based on the measurement parameters of each successive measurement, measuring a performance indicator of each successive measurement, and determining at least one actuation characteristic based on the first measurement parameter of the measurement having the highest performance indicator.

Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A clock extracted from a first sequence of symbols transmitted on a first lane of a multi-lane interface is used to receive and decode the first sequence of symbols and to receive and decode data and/or symbols transmitted on a second lane of the multilane interface. The clock signal may be derived from transitions in the signaling state of N wires between consecutive pairs of symbols in the first sequence of symbols. The first lane may be encoded using N! encoding and the second lane may be a serial or N! link.

Abstract: System, methods and apparatus are described that facilitate communication of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A receiving device receives a sequence of symbols over a multi-wire link. The receiving device further receives a clock signal via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link. The receiving device decodes the sequence of symbols using the clock signal. In an aspect, a second clock signal is embedded in guaranteed transitions between pairs of consecutive symbols in the sequence of symbols. Accordingly, the receiving device decodes the sequence of symbols using the clock signal received via the dedicated clock line while ignoring the second clock signal.

Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A sequence of data bits is converted into M transition numbers, which are then converted into a sequence of symbols. The sequence of symbols is transmitted received over N wires. A clock signal may be effectively embedded in the transmission of the sequence of symbols. Each of the sequence of symbols may be selected based on a corresponding one of the M transition numbers and a value of a preceding one of the sequence of symbols.

Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A clock extracted from a first sequence of symbols transmitted on a first lane of a multi-lane interface is used to receive and decode the first sequence of symbols and to receive and decode data and/or symbols transmitted on a second lane of the multi-lane interface. The clock signal may be derived from transitions in the signaling state of N wires between consecutive pairs of symbols in the first sequence of symbols. The first lane may be encoded using N! encoding and the second lane may be a serial or N! link.

Abstract: System, methods and apparatus are described that provide an N-factorial (N!) voltage-mode driver. A method communicating on an N! interface includes encoding data in a symbol to be transmitted over the N wires of the interface, and for each wire of the N wires, calculating a resultant current for the wire by summing current flows defined for two or more two-wire combinations that include the wire, and coupling a switchable voltage source to the each wire. Each bit in the symbol defines a current flow between a pair of the N wires that is one of a plurality of possible two-wire combinations of the N wires.

Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. Each symbol in a sequence of symbols received from a plurality of signal wires is received in an odd transmission interval or an even transmission interval. A first clock signal is generated from transitions in signaling state of the wires occurring between each odd transmission interval and a consecutive even transmission interval. A second clock signal is generated from transitions in signaling state of the plurality of wires occurring between each even transmission interval and a consecutive odd transmission interval. The first and second clock signals are used to capture symbols received in even and odd transmission intervals, respectively.

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. Each of the three terminals may be driven such that transistors are activated to couple a terminal to first and second voltage levels through a pair of impedances when the terminal would otherwise be undriven. The terminal is then pulled toward an intermediate voltage level while the terminal presents a desired impedance level to a transmission line.

Abstract: System, methods and apparatus are described that offer improved performance of a camera control interface (CCIe) bus. A method of data communications includes transmitting a first synchronization code on a serial bus, establishing synchronization with a first device coupled to the serial bus in response to the first synchronization code, communicating with the first device over the serial bus in accordance with a first protocol, after establishing synchronization with the first device, transmitting a first unsynchronization code on the serial bus, where the unsynchronization code is configured to cause a loss of synchronization with the first device, transmitting a second synchronization code on the serial bus, establishing synchronization with a second device coupled to the serial bus in response to the second synchronization code, and communicating with the second device over the serial bus in accordance with a second protocol, after establishing synchronization with the second device.

Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A clock extracted from a first sequence of symbols transmitted on a first lane of a multi-lane interface is used to receive and decode the first sequence of symbols and to receive and decode data and/or symbols transmitted on a second lane of the multi-lane interface. The clock signal may be derived from transitions in the signaling state of N wires between consecutive pairs of symbols in the first sequence of symbols. The first lane may be encoded using N! encoding and the second lane may be a serial or N! link.