Abstract: System, methods and apparatus are described that offer improved performance of an Inter-Integrated Circuit (I2C) bus. Primary data may be encoded in first signaling in accordance with I2C bus protocols, and the first signaling may be combined with second signaling to obtain combined signaling for transmission on an I2C bus. Secondary data may be encoded in the second signaling with the combined signaling remaining compatible with the I2C bus protocols. The second signaling may modulate a voltage level of at least one signal in the first signaling. The second signaling may pulse-width modulate a clock signal transmitted on the I2C bus. The second signaling may modify a start condition between bytes transmitted on the I2C bus. The second signaling may add a plurality of short pulses to a clock signal transmitted in the first signaling.

Abstract: System, methods and apparatus are described that offer improved performance of an Inter-Integrated Circuit (I2C) bus. Primary data may be encoded in first signaling in accordance with I2C bus protocols, and the first signaling may be combined with second signaling to obtain combined signaling for transmission on an I2C bus. Secondary data may be encoded in the second signaling with the combined signaling remaining compatible with the I2C bus protocols. The second signaling may modulate a voltage level of at least one signal in the first signaling. The second signaling may pulse-width modulate a clock signal transmitted on the I2C bus. The second signaling may modify a start condition between bytes transmitted on the I2C bus. The second signaling may add a plurality of short pulses to a clock signal transmitted in the first signaling.

Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A data payload may be converted to a set of transition numbers, the transition numbers may be converted to a sequence of symbols and an error correction code (ECC) may be calculated from symbols in the sequence of symbols. The ECC corresponds to the data payload and the ECC may be appended to the data payload such that the set of transition numbers includes transition numbers corresponding to the ECC. The sequence of symbols is then transmitted on a plurality of signal wires. Clock information is encoded in the sequence of symbols. The clock information may be encoded by ensuring that each pair of consecutive symbols in the sequence of symbols includes two symbols that produce different signaling states on the plurality of signal wires.

Abstract: Various aspects directed towards facilitating an error detection optimization over a shared bus are disclosed. A master device is coupled to a slave device, and an encoded communication of a word is facilitated between the master device and the slave device via a control data bus. The encoded communication is encoded according to a protocol that allocates a plurality of least significant bits of the encoded communication to facilitate maximizing an error detection constant. The protocol allocates the plurality of least significant bits to include at least one additional error detection bit or at least a first most significant bit of a data portion of the word.

Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A sequence of data bits is converted into M transition numbers, which are then converted into a sequence of symbols. The sequence of symbols is transmitted received over N wires. A clock signal may be effectively embedded in the transmission of the sequence of symbols. Each of the sequence of symbols may be selected based on a corresponding one of the M transition numbers and a value of a preceding one of the sequence of symbols.

Abstract: A device is provided comprising a bus, a first set of devices, and a second set of devices. The first set of devices is coupled to the bus and configured to communicate over the bus according to a first communication protocol. The second set of devices is coupled to the bus and configured to communicate over the bus according to both the first communication protocol and a second communication protocol. In a first mode of operation, the first set of devices and second set of devices may concurrently communicate over the bus using the first communication protocol. In a second mode of operation, the second set of devices communicate with each other using the second communication protocol over the bus, and the first set of devices to stop operating on the bus.

Abstract: A device may include an interface to couple to a multi-mode bus shared with one or more I2C-compatible devices. The bus may include a first line and a second line, wherein in a first mode of operation the first line transmits data and the second line transmits a clock, while in a second mode of operation the first and second lines are both used to transmit data. The device may also include a transmitter to transmit data over the bus (SDA line 3204 and SCL line 3206) as a sequence of pulses within symbol slots. In the second mode of operation a transmission period of a first symbol slot is stretched to prevent the I2C-compatible devices from changing into an unpredictable state as a result of a transition from a first pulse to a second pulse.

Abstract: Systems, methods and apparatus extract data and clocks from a multi-wire bus that includes a first lane operated in accordance with a camera control interface (CCIe) mode of operation or a first lane operated in accordance with an N! mode of operation. Timing information derived from a sequence of symbols received from the first lane may be used to deserialize data received on a second lane of the multi-wire bus or decode a sequence of symbols received on the second lane. The symbols in a pair of consecutive symbols transmitted on the first lane cause different signaling states. Data on the second lane may be deserialized using on the receive clock derived from the timing information. In a CCIe lane, the final symbol of the sequence of symbols may be suppressed or a setup condition curtailed when the final symbol produces a signaling state equivalent to the setup condition.

Abstract: Master and slave devices may be coupled to a control data bus. A method includes controlling data transmissions over a bus from a master device, where data bits are transcoded into symbols for transmission across two lines of the bus and a clock signal is embedded within symbol transitions of the data transmissions, and providing an interrupt period, during which one or more slave devices coupled to the bus can assert an interrupt request on a first line of the bus, within part of a heartbeat transmission by the master device over the first line and a second tine of the bus. The interrupt request may be an indicator that the asserting slave device wishes to request some action by the master device.

Abstract: Master and slave devices may be coupled to a control data bus. A method includes controlling data transmissions over a bus using a master device. A clock signal is provided by the master device on a clock line (SCL) of a serial bus, a receive clock generated from transitions on the SCL line when a slave device is transmitting data on the SDA line, is calibrated using a delay based on a duration of time measured between an edge of the clock signal provided on the SCL line and at least one transition produced on the SDA line by a slave device in response to the edge of the clock signal. Data, including double data rate data, may be reliably received using the calibrated receive clock.

Abstract: Systems, methods and apparatus are described for use in a communications link having a number of connectors. A method for communication using differential signaling with symbol transition clocking signaling communicates symbols over a communications link without transmitting a clock signal in a dedicated lane of the communications link. At a receiver, clock information may be extracted without using a phase-locked loop. The method includes converting data bits into a plurality of transition numbers, converting the plurality of transition numbers into a sequence of symbols, and transmitting the sequence of symbols over a plurality of signal wires. A clock signal may be embedded in transitions between consecutive symbols in the sequence of symbols. Each consecutive pair of transition numbers in the plurality of transition numbers may include two transition numbers that are different from one another. The sequence of symbols may be transmitted as a plurality of differential signals.

Abstract: A termination network circuit for a differential signal transmitter comprises a plurality of n resistance elements and a plurality of differential signal drivers. A first end of each of the resistance elements is coupled at a common node, where n is an integer value and is the number of conductors used to transmit a plurality of differential signals. Each differential signal driver may include a positive terminal driver and a negative terminal driver. The positive terminal driver is coupled to a second end of a first resistance element while the negative terminal driver is coupled to a second end of a second resistance element. The positive terminal driver and the negative terminal driver are separately and independently switchable to provide a current having a magnitude and direction. During a transmission cycle each of the resistance elements has a current of a different magnitude and/or direction than the other resistance elements.

Abstract: Methods, apparatus, and computer program products are described, which provide a mechanism that enables data to be written into registers of a slave device without a free-running clock, while facilitating an efficient sleep and wakeup mechanism for slave devices. A receiver device may receive a plurality of symbols over a shared bus, extract a receive clock signal embedded in symbol-to-symbol transitions of the plurality of symbols, convert the plurality of symbols into a transition number, convert the transition number into data bits, and store at least a portion of the data bits into one or more registers using only the receive clock signal. The receiver device may start a down counter upon detection of a first cycle of the clock signal, trigger a marker when the down counter reaches a pre-defined value, and use the marker to store at least a portion of the data bits into registers.

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. An address list may associate each of a plurality of slave devices coupled to a control data bus with a plurality of slave device identifiers. Access to the control data bus may be controlled based on the address list such that, in a first mode of operation information may be broadcast to multiple slave devices using a first group slave device identifier and, in a second mode of operation, information may be exchanged with a single slave device using an individualized slave device identifier.

Abstract: System, methods and apparatus are described for extracting data and clocks from a camera control interface bus. A transmit clock may be generated while transmitting symbols on the bus, and a receive clock may be extracted when receiving symbols from the bus. A heartbeat clock may be extracted by from symbols transmitted on the bus when the apparatus is not transmitting or receiving symbols. The transmit clock may be used to encode data in a sequence of symbols for transmission on a pair of connectors of the bus. The receive clock may be extracted by detecting transitions occurring between symbols transmitted on the bus, and generating the receive clock based on the transitions. The heartbeat clock may be used to control operations of the apparatus, or synchronize one or more function of the apparatus. The heartbeat clock may be encoded in a control word transmitted on the bus.

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two or more devices within an electronic apparatus. Embodiments disclosed herein relate to scanning for slave identifiers (SIDs) on a CCIe bus. A disclosed method includes transmitting a first inquiry on a control data bus, where the first inquiry includes a first configuration of bits, determining presence of a slave device that has a slave identifier that includes a second configuration of bits that matches the first configuration of bits, and repetitively transmitting additional inquiries on the control data bus with different configurations of bits until all bits of the slave identifier are determined The slave device may assert a response to each inquiry that includes a configuration of bits that matches a corresponding configuration of bits in the slave identifier.

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A first transition may be detected in a signal carried on a data lane of a data communications link or carried on a timing lane of the data communications link and an edge may be generated on a receiver clock signal based on the first transition. Data may be captured from the data lane using the receiver clock signal. The timing lane may carry a clock signal, a strobe signal or another signal providing timing information. The strobe signal may transition between signaling states when no state transition occurs on any of a plurality of data lanes at a boundary between consecutive data periods.

Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. Each symbol in a sequence of symbols received from a plurality of signal wires is received in an odd transmission interval or an even transmission interval. A first clock signal is generated from transitions in signaling state of the wires occurring between each odd transmission interval and a consecutive even transmission interval. A second clock signal is generated from transitions in signaling state of the plurality of wires occurring between each even transmission interval and a consecutive odd transmission interval. The first and second clock signals are used to capture symbols received in even and odd transmission intervals, respectively.

Abstract: A plurality of slave devices is coupled to a control data bus along with at least one master device that is managing access of slave devices to the control data bus. At least one slave device operates in a sI2C protocol mode of operation and at least one other slave device operates in a CCIe mode of operation. At least the slave devices using sI2C protocol mode use the control data bus for interrupt requests. In order to maintain the integrity of CCIe communications, the slave devices using the sI2C protocol mode disables issuing IRQs when the control data bus operates according to the CCIe mode.

Abstract: A device is provided comprising a shared bus, a slave device, and a master device. The slave device may be coupled to the shared bus. The master device may be coupled to the control data bus and adapted to manage communications on the shared bus. Transmissions over the shared bus are a plurality of bits that are encoded into ternary numbers which are then transcoded into symbols for transmission, and either the 3 least significant bits or the least significant in the plurality of bits are used for error detection of the transmission.