Abstract: A method for making an array of photodiodes with more uniform optical spectral response for the red, green, and blue pixel cells on a CMOS color imager is achieved. After forming a field oxide on a substrate to electrically isolate device areas for CMOS circuits, an array of deep N doped wells is formed for photodiodes for the long wavelength red pixel cells. An array of P doped well regions is formed adjacent to and interlaced with the N doped wells. Shallow diffused N+ regions are formed within the P doped wells for the shorter wavelength green and blue color pixels cells. The shallow diffused photodiodes improve the quantum efficiency (QE), and provide a color imager with improved color fidelity. An insulating layer and appropriate dye materials are deposited and patterned over the photodiodes to provide the array of color pixel cells. The N and P doped wells are also used for the supporting FET CMOS circuits to provide a cost-effective manufacturing process.

Abstract: A new method to form CMOS image sensors in the manufacture of an integrated circuit device is achieved. The method comprises providing a semiconductor substrate. Sensor diodes are formed in the semiconductor substrate each comprising a first terminal and a second terminal. Gates are formed for transistors in the CMOS image sensors. The gates comprise a conductor layer overlying the semiconductor substrate with an insulating layer therebetween. The transistors include reset transistors. Ions are implanted into the semiconductor substrate to form source/drain regions for the transistors. The source regions of the reset transistors are formed in the first terminals of the sensor diodes. Ions are implanted into the reset transistor sources to form double diffused sources. The implanting is blocked from other source/drain regions.

Abstract: An SRAM device has STI regions separated by mesas and doped regions including source/drain regions, active areas, wordline conductors and contacts in a semiconductor substrate is made with a source region has 90° transitions in critical locations. Form a dielectric layer above the active areas. Form the wordline conductors above the active areas transverse to the active areas. The source and drain regions of a pass gate transistor are on the opposite sides of a wordline conductor. Form the sidewalls along the <100> crystal plane. Form the contacts extending down through to the dielectric layer to the mesas. Substrate stress is reduced because the large active area region formed in the substrate assures that the contacts are formed on the <100> surfaces of the mesas are in contact with the mesas formed on the substrate and that the <110> surfaces of the silicon of the mesas are shielded from the contacts.

Abstract: A method for making an array of photodiodes with more uniform optical spectral response for the red, green, and blue pixel cells on a CMOS color imager is achieved. After forming a field oxide on a substrate to electrically isolate device areas for CMOS circuits, an array of deep N doped wells is formed for photodiodes for the long wavelength red pixel cells. An array of P doped well regions is formed adjacent to and interlaced with the N doped wells. Shallow diffused N+ regions are formed within the P doped wells for the shorter wavelength green and blue color pixels cells. The shallow diffused photodiodes improve the quantum efficiency (QE), and provide a color imager with improved color fidelity. An insulating layer and appropriate dye materials are deposited and patterned over the photodiodes to provide the array of color pixel cells. The N and P doped wells are also used for the supporting FET CMOS circuits to provide a cost-effective manufacturing process.

Abstract: A method of fabricating a stripe photodiode element, for an image sensor cell, has been developed. The stripe photodiode element is comprised of a narrow width, serpentine shaped, lightly doped N type region, in a P well region. The use of the serpentine shaped region results in increased photon collection area, when compared to counterparts fabricated using non-serpentine shaped patterns. In addition the use of the serpentine shaped N type regions allow both vertical, as well as horizontal depletion regions, to result, thus increasing the quantum efficiency of the photodiode element. The combination of narrow width, and a reduced dopant level, for the N type serpentine shaped region, result in a fully depleted photodiode element.

Abstract: A method for making an array of photodiodes with more uniform optical spectral response for the red, green, and blue pixel cells on a CMOS color imager is achieved. After forming a field oxide on a substrate to electrically isolate device areas for CMOS circuits, an array of deep N doped wells is formed for photodiodes for the long wavelength red pixel cells. An array of P doped well regions is formed adjacent to and interlaced with the N doped wells. Shallow diffused N+ regions are formed within the P doped wells for the shorter wavelength green and blue color pixels cells. The shallow diffused photodiodes improve the quantum efficiency (QE), and provide a color imager with improved color fidelity. An insulating layer and appropriate dye materials are deposited and patterned over the photodiodes to provide the array of color pixel cells. The N and P doped wells are also used for the supporting FET CMOS circuits to provide a cost-effective manufacturing process.

Abstract: A method is disclosed for forming multilayered self-aligned gate electrodes having uniform silicide layer. It is shown that by using amorphous silicon of a certain thickness with or without polysilicon as an underlayer material, the salicide structure so formed has improved gate characteristics.

Abstract: A process for making improved borderless contact structure to salicide field effect transistors (FETs) has been achieved. Salicide FETs are formed on device areas surrounded by a shallow trench isolation (STI) using a first rapid thermal anneal (RTA-1) to form a metal silicide on the source/drain contacts and the gate electrodes, and a second rapid thermal anneal (RTA-2) is delayed until after forming a borderless contact opening structures to the source/drain areas of the FETs. An etch stop (Si3N4) layer and an interlevel dielectric (ILD) layer is deposited, and borderless contact openings, extending over the STI, are etched in the ILD and etch stop layers to the source/drain areas. The contact openings across the substrate must be overetched to insure that all contacts are open. This results in over-etched region in the STI at the source/drain-STI interface that result in source/drain-to-substrate shorts when metal plugs are formed in the contact openings.

Abstract: A method of fabricating a stripe photodiode element, for an image sensor cell, has been developed. The stripe photodiode element is comprised of a narrow width, serpentine shaped, lightly doped N type region, in a P well region. The use of the serpentine shaped region results in increased photon collection area, when compared to counterparts fabricated using non-serpentine shaped patterns. In addition the use of the serpentine shaped N type regions allow both vertical, as well as horizontal depletion regions, to result, thus increasing the quantum efficiency of the photodiode element. The combination of narrow width, and a reduced dopant level, for the N type serpentine shaped region, result in a fully depleted photodiode element.

Abstract: A method for forming a high performance photodiode with tightly-controlled junction profile for CMOS image sensor with STI process. The following steps are performed: providing a substrate; forming a hard mask layer for defining a pattern on the substrate; etching the substrate on the surface of the substrate not covered by the hard mask layer to form a shallow trench; growing an oxide lining in the shallow trench by a thermal oxidation process; performing a first thermal annealing; defining an n-well region in the shallow trench; implanting the n-well region; performing a second thermal annealing; forming a silicon oxide layer on the substrate to fill in the shallow trench; removing a portion of the silicon oxide layer on the substrate such that the portion in the shallow trench remains; removing the hard mask layer; and forming a transistor on the substrate, wherein the transistor comprises a gate structure, a source region, and a drain region.

Abstract: A method to form shallow trench isolations with reduced substrate defects by using a nitrogen anneal is achieved. A silicon substrate is provided. The silicon substrate is etched where not protected by a photoresist mask to form shallow trenches where shallow trench isolations are planned. A liner oxide layer is grown on the interior surfaces of the shallow trenches. The silicon substrate and the liner oxide layer are annealed to reduce or eliminate defects, dislocations, interface traps, and stress in the silicon substrate. An isolation oxide layer is deposited overlying the liner oxide layer and completely filling the shallow trenches. The isolation oxide layer is etched down to the top surface of the silicon substrate and thereby forms the shallow trench isolations. The integrated circuit device is completed.

Abstract: A buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the semiconductor substrate to fill the gaps. The hard mask layer is removed. The polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted to form the buried contact. A refractory metal layer is deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines and planarized to form polycide gate electrodes and interconnection lines.

Abstract: A process for making improved borderless contact structure to salicide field effect transistors (FETs) has been achieved. Salicide FETs are formed on device areas surrounded by a shallow trench isolation (STI) using a first rapid thermal anneal (RTA-1) to form a metal silicide on the source/drain contacts and the gate electrodes, and a second rapid thermal anneal (RTA-2) is delayed until after forming a borderless contact opening structures to the source/drain areas of the FETs. An etch stop (Si3N4) layer and an interlevel dielectric (ILD) layer is deposited, and borderless contact openings, extending over the STI, are etched in the ILD and etch stop layers to the source/drain areas. The contact openings across the substrate must be over-etched to insure that all contacts are open. This results in over-etched region in the STI at the source/drain-STI interface that result in source/drain-to-substrate shorts when metal plugs are formed in the contact openings.

Abstract: A process for fabricating a lateral photodiode element, for an image sensor cell, with an increased depletion region, has been developed. The process features protecting a portion of the semiconductor substrate from ion implantation procedures used to create the P well, and the N well components of the lateral photodiode element. The protected region, or the space between the P well and N well regions, allows a larger depletion region to be realized, when compared to lateral photodiode elements in which the N well and P well regions butt. The space between the P well and N well regions, between about 0.2 to 0.4 um, result in the desired P well—intrinsic or P type semiconductor substrate—N well, (P-I-N), lateral photodiode element.

Abstract: A method of fabricating a stripe photodiode element, for an image sensor cell, has been developed. The stripe photodiode element is comprised of a narrow width, serpentine shaped, lightly doped N type region, in a P well region. The use of the serpentine shaped region results in increased photon collection area, when compared to counterparts fabricated using non-serpentine shaped patterns. In addition the use of the serpentine shaped N type regions allow both vertical, as well as horizontal depletion regions, to result, thus increasing the quantum efficiency of the photodiode element. The combination of narrow width, and a reduced dopant level, for the N type serpentine shaped region, result in a fully depleted photodiode element.

Abstract: A method for integrating salicide and borderless contact processes while avoiding current leakage at the shallow trench isolation edge is described. Shallow trench isolation (STI) regions are formed in a semiconductor substrate electrically isolating an active area from other active areas. A gate electrode and associated source and drain regions are formed in the active area wherein dielectric spacers are formed on sidewalls of the gate electrode. A metal layer is deposited over the gate electrode and associated source and drain regions. A first annealing of the semiconductor substrate transforms the metal layer into a metal silicide layer over the gate electrode and source and drain regions. The metal layer which is not transformed into a metal silicide overlying the dielectric spacers and shallow trench isolation regions is removed. An etch stop layer is deposited over the surface of the semiconductor substrate.

Abstract: A new method of forming a polysilicon resistor having precisely controlled resistance by using a thin silicon nitride cap over the polysilicon resistor is described. A dielectric layer is provided on a semiconductor substrate. A polysilicon layer is deposited overlying the dielectric layer and patterned to form a polysilicon resistor. A silicon nitride capping layer having a thickness of not more than 100 Angstroms is deposited overlying the polysilicon resistor and dielectric layer. An interlevel dielectric layer is deposited overlying the silicon nitride capping layer. The substrate is annealed thereby densifying the silicon nitride capping layer. A self-aligned contact opening may be made through the interlevel dielectric layer, the silicon nitride capping layer, and the dielectric layer to underlying device structures. The capping silicon nitride layer is thin enough not to act as an etch stop in the self-aligned contact etching. The contact opening is filled with a conducting layer.

Abstract: A method for fabricating a novel plug structure for low resistance ohmic stacked contacts and at the same time forming metal contacts to devices on a SRAM cell was achieved. The method involved forming electrically conductive plugs in the stacked contact openings to form ohmic connections between a P+ doped polysilicon layer and a N+ doped polysilicon layer and thereby increasing the on current (Ion) of the SRAM cell. The electrical conductive plugs are also simultaneously formed in metal contact openings to devices areas elsewhere on the substrate. The process for the plug structure also reduces the mask set by one masking level over the prior art process.

Abstract: A method of providing a chemical mechanical polishing planarization process for preventing multi-polysilicon and multi-metal level electrical shorts, which includes briefly the sequential processing steps of i) providing an insulating layer to a first thickness over a device wafer with non-planar surface topography; ii) chemical-mechanical polishing the first insulating layer; and iii) deposition of another polysilicon layer of second thickness to prevent the barely exposed or exposed underlying polysilicon from shorting to the next polysilicon or metal level of interconnects.

Abstract: A process for integrating the formation of salicided, CMOS logic devices, for a CMOS logic circuit region, and of a non-salicided, photodiode element, for a image sensor cell region, has been developed. The process features the selective formation of a thin silicon oxide layer on the top surface of the photodiode element, in the image sensor cell region of a semiconductor chip. The thin silicon oxide layer prevents formation of metal silicide on the photodiode element, during the procedure used to form the desired metal silicide layer on the CMOS logic devices, thus allowing low dark current generation, and a high signal to noise ratio, to be obtained via the non-salicided, photodiode element. A thick organic layer, is used to protect the thin silicon oxide layer, located on the photodiode element, during the procedure used to remove regions of the thin silicon oxide layer from the surfaces of elements to be subsequently overlaid with metal silicide.