Patents by Inventor Shou-Wei Hsieh
Shou-Wei Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105720Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.Type: ApplicationFiled: December 1, 2023Publication date: March 28, 2024Applicant: United Microelectronics Corp.Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
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Patent number: 11876095Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.Type: GrantFiled: July 5, 2021Date of Patent: January 16, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
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Publication number: 20230145660Abstract: An NMOS structure includes a semiconductor substrate, a dielectric structure, a source doped region, a drain doped region, a channel region, a gate structure and two isolation P-type wells. The dielectric structure is formed in the semiconductor substrate to define an active region, in which the source/drain doped region and the channel region are formed. The channel region includes two opposite first sides and two opposite second sides. The source/drain doped region is respectively formed between the two second sides and the dielectric structure. The gate structure is formed on the semiconductor substrate. The gate structure covers a part of the dielectric structure beside the first sides. The two isolation P-type wells are formed in a part of the dielectric structure not covered by the gate structure. The isolation P-type wells respectively surround a periphery of the source/drain doped region and end at the respective second side.Type: ApplicationFiled: December 1, 2021Publication date: May 11, 2023Inventors: Hau-Yuan Huang, Chia-Chen Tsai, Jia-Bin Yeh, Shou-Wei Hsieh
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Publication number: 20230143927Abstract: A semiconductor device includes a gate isolation structure on a shallow trench isolation (STI), a first epitaxial layer on one side of the gate isolation structure, a second epitaxial layer on another side of the gate isolation structure, first fin-shaped structures directly under the first epitaxial layer, and second fin-shaped structures directly under the second epitaxial layer, in which the STI surrounds the first fin-shaped structures and the second fin-shaped structures.Type: ApplicationFiled: January 5, 2023Publication date: May 11, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
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Publication number: 20230129579Abstract: A high electron mobility transistor (HEMT) device including a substrate, a channel layer, a barrier layer, a p-type gallium nitride (GaN) spacer, a gate electrode, a source electrode, and a drain electrode is provided. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer and has a protruding portion. The P-type GaN spacer is disposed on a side wall of the protruding portion. The gate electrode is disposed on the protruding portion and the P-type GaN spacer. The source electrode and the drain electrode are disposed on two sides of the gate electrode.Type: ApplicationFiled: November 16, 2021Publication date: April 27, 2023Applicant: United Microelectronics Corp.Inventors: Hao-Ming Lee, Ta Kang Lo, Tsai-Fu Chen, Shou-Wei Hsieh
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Publication number: 20230066954Abstract: A semiconductor device includes a gate structure on a substrate, a single diffusion break (SDB) structure adjacent to the gate structure, a first spacer adjacent to the gate structure, a second spacer adjacent to the SDB structure, a source/drain region between the first spacer and the second spacer, an interlayer dielectric (ILD) layer around the gate structure and the SDB structure, and a contact plug in the ILD layer and on the source/drain region. Preferably, a top surface of the second spacer is lower than a top surface of the first spacer.Type: ApplicationFiled: November 9, 2022Publication date: March 2, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
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Patent number: 11581422Abstract: A semiconductor device includes a gate isolation structure on a shallow trench isolation (STI), a first epitaxial layer on one side of the gate isolation structure, a second epitaxial layer on another side of the gate isolation structure, first fin-shaped structures directly under the first epitaxial layer, and second fin-shaped structures directly under the second epitaxial layer, in which the STI surrounds the first fin-shaped structures and the second fin-shaped structures.Type: GrantFiled: January 29, 2021Date of Patent: February 14, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
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Patent number: 11527638Abstract: A method for fabricating semiconductor device includes: forming a fin-shaped structure on a substrate, wherein the fin-shaped structure is extending along a first direction; forming a gate layer on the fin-shaped structure; removing part of the gate layer and part of the fin-shaped structure to form a first trench for dividing the fin-shaped structure into a first portion and a second portion, wherein the first trench is extending along a second direction; forming a patterned mask on the gate layer and into the first trench; removing part of the gate layer to form a second trench, wherein the second trench is extending along the first direction; and filling a dielectric layer in the first trench and the second trench.Type: GrantFiled: January 29, 2021Date of Patent: December 13, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
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Publication number: 20210335786Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.Type: ApplicationFiled: July 5, 2021Publication date: October 28, 2021Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
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Patent number: 11088137Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.Type: GrantFiled: December 23, 2019Date of Patent: August 10, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
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Publication number: 20210210628Abstract: A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.Type: ApplicationFiled: March 22, 2021Publication date: July 8, 2021Inventors: Cheng-Han Wu, Hsin-Yu Chen, Chun-Hao Lin, Shou-Wei Hsieh, Chih-Ming Su, Yi-Ren Chen, Yuan-Ting Chuang
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Publication number: 20210167189Abstract: A semiconductor device includes a gate isolation structure on a shallow trench isolation (STI), a first epitaxial layer on one side of the gate isolation structure, a second epitaxial layer on another side of the gate isolation structure, first fin-shaped structures directly under the first epitaxial layer, and second fin-shaped structures directly under the second epitaxial layer, in which the STI surrounds the first fin-shaped structures and the second fin-shaped structures.Type: ApplicationFiled: January 29, 2021Publication date: June 3, 2021Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
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Publication number: 20210159322Abstract: A method for fabricating semiconductor device includes: forming a fin-shaped structure on a substrate, wherein the fin-shaped structure is extending along a first direction; forming a gate layer on the fin-shaped structure; removing part of the gate layer and part of the fin-shaped structure to form a first trench for dividing the fin-shaped structure into a first portion and a second portion, wherein the first trench is extending along a second direction; forming a patterned mask on the gate layer and into the first trench; removing part of the gate layer and part of the fin-shaped structure to form a second trench, wherein the second trench is extending along the first direction; and filling a dielectric layer in the first trench and the second trench.Type: ApplicationFiled: January 29, 2021Publication date: May 27, 2021Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
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Patent number: 10991824Abstract: A semiconductor device includes: a fin-shaped structure on the substrate; a shallow trench isolation (STI) around the fin-shaped structure; a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure; a second gate structure on the STI; and a third gate structure on the SDB structure, wherein a width of the third gate structure is greater than a width of the second gate structure.Type: GrantFiled: January 21, 2019Date of Patent: April 27, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Cheng-Han Wu, Hsin-Yu Chen, Chun-Hao Lin, Shou-Wei Hsieh, Chih-Ming Su, Yi-Ren Chen, Yuan-Ting Chuang
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Patent number: 10943993Abstract: A method for fabricating semiconductor device includes: forming a fin-shaped structure on a substrate, wherein the fin-shaped structure is extending along a first direction; forming a gate layer on the fin-shaped structure; removing part of the gate layer and part of the fin-shaped structure to form a first trench for dividing the fin-shaped structure into a first portion and a second portion, wherein the first trench is extending along a second direction; forming a patterned mask on the gate layer and into the first trench; removing part of the gate layer and part of the fin-shaped structure to form a second trench, wherein the second trench is extending along the first direction; and filling a dielectric layer in the first trench and the second trench.Type: GrantFiled: April 29, 2019Date of Patent: March 9, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
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Publication number: 20200312984Abstract: A method for fabricating semiconductor device includes: forming a fin-shaped structure on a substrate, wherein the fin-shaped structure is extending along a first direction; forming a gate layer on the fin-shaped structure; removing part of the gate layer and part of the fin-shaped structure to form a first trench for dividing the fin-shaped structure into a first portion and a second portion, wherein the first trench is extending along a second direction; forming a patterned mask on the gate layer and into the first trench; removing part of the gate layer and part of the fin-shaped structure to form a second trench, wherein the second trench is extending along the first direction; and filling a dielectric layer in the first trench and the second trench.Type: ApplicationFiled: April 29, 2019Publication date: October 1, 2020Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
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Publication number: 20200203523Abstract: A semiconductor device includes: a fin-shaped structure on the substrate; a shallow trench isolation (STI) around the fin-shaped structure; a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure; a second gate structure on the STI; and a third gate structure on the SDB structure, wherein a width of the third gate structure is greater than a width of the second gate structure.Type: ApplicationFiled: January 21, 2019Publication date: June 25, 2020Inventors: Cheng-Han Wu, Hsin-Yu Chen, Chun-Hao Lin, Shou-Wei Hsieh, Chih-Ming Su, Yi-Ren Chen, Yuan-Ting Chuang
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Patent number: 10692780Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first gate structure on the first region and a second gate structure on the second region; forming a first spacer around the first gate structure; forming a first epitaxial layer adjacent to two sides of the first spacer; forming a buffer layer on the first gate structure; and forming a contact etch stop layer (CESL) on the buffer layer on the first region and the second gate structure on the second region.Type: GrantFiled: February 20, 2019Date of Patent: June 23, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
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Publication number: 20200144256Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.Type: ApplicationFiled: December 23, 2019Publication date: May 7, 2020Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
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Patent number: 10566327Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.Type: GrantFiled: August 30, 2017Date of Patent: February 18, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh