Abstract: A non-volatile memory cell having a local silicon nitride layer to control dispersion of hot electrons is disclosed. The dual-bit non-volatile memory cell has a stack of layers including silicon on the surface of a substrate. The stack of layers has at least one first oxide silicon layer and a silicon nitride layer overlying the first oxide silicon layer. An opening is formed in the stack of layers and a gate oxide layer is deposited on the surface of the substrate within the opening. A control gate is formed on the gate oxide layer followed by a second oxide silicon layer overlying the surfaces of the control gate and the stack of layers. A second polysilicon layer is formed overlying the gate oxide layer. Dual split-gates are then formed on the second polysilicon layer.

Abstract: A non-volatile memory cell having a local silicon nitride layer to control dispersion of hot electrons is disclosed. The dual-bit non-volatile memory cell has a stack of layers including silicon on the surface of a substrate. The stack of layers has at least one first oxide silicon layer and a silicon nitride layer overlying the first oxide silicon layer. An opening is formed in the stack of layers and a gate oxide layer is deposited on the surface of the substrate within the opening. A control gate is formed on the gate oxide layer followed by a second oxide silicon layer overlying the surfaces of the control gate and the stack of layers. A second polysilicon layer is formed overlying the gate oxide layer. Dual split-gates are then formed on the second polysilicon layer.

Abstract: A non-volatile memory cell having a local silicon nitride layer to control dispersion of hot electrons is disclosed. The dual-bit non-volatile memory cell has a stack of layers including silicon on the surface of a substrate. The stack of layers has at least one first oxide silicon layer and a silicon nitride layer overlying the first oxide silicon layer. An opening is formed in the stack of layers and a gate oxide layer is deposited on the surface of the substrate within the opening. A control gate is formed on the gate oxide layer followed by a second oxide silicon layer overlying the surfaces of the control gate and the stack of layers. A second polysilicon layer is formed overlying the gate oxide layer. Dual split-gates are then formed on the second polysilicon layer.

Abstract: Steep spacer is formed by using depositing and etching of dual conformal layers. A first conformal dielectric layer is deposited on a substrate with a gate electrode structure formed thereon. Then, a second conformal layer is deposited on the first conformal dielectric layer. The second conformal layer is anisotropically etched to form a first spacer on the sidewall of the first conformal dielectric layer. Next, the first conformal layer is anisotropically etched by using the first spacer as a mask to form a second spacer on the sidewall of the gate electrode structure. Then, the first spacer is removed and the second spacer is steep.

Abstract: Steep spacer is formed by using depositing and etching of dual conformal layers. A first conformal dielectric layer is deposited on a substrate with a gate electrode structure formed thereon. Then, a second conformal layer is deposited on the first conformal dielectric layer. The second conformal layer is anisotropically etched to form a first spacer on the sidewall of the first conformal dielectric layer. Next, the first conformal layer is anisotropically etched by using the first spacer as a mask to form a second spacer on the sidewall of the gate electrode structure. Then, the first spacer is removed and the second spacer is steep.

Abstract: A method of fabricating a flash memory is disclosed: firstly, a P-type silicon substrate is divided into a PMOS area, an NMOS area, and a flash memory area. The first polysilicon layer and the first oxide layer are formed at the flash memory area. Thereafter, the second polysilicon layer, the second oxide layer, and a layer of TEOS are formed. The first photo resist is then formed to define the gate pattern of the flash cell array, and then a process of N+ ion implantation is performed to form the source and drain of the flash cell array. After stripping the first photo resist, the second photo resist is formed to define the gate pattern at the NMOS area, and a process of N+ ion implantation is performed to form the NLDD structure. After stripping the second photo resist, the first sidewall is formed, and then a process of N− ion implantation is performed to form the NMOS source/drain. The third photo resist is then formed to define the gate pattern at the PMOS area.

Abstract: A method of making dual-gate structure with only three masking steps is provided.