Abstract: A method for fabricating semiconductor device includes the steps of first forming a metal gate on a substrate and a spacer around the metal gate, in which the metal gate comprises a high-k dielectric layer, a work function metal layer, and a low-resistance metal layer. Next, part of the high-k dielectric layer is removed to form an air gap between the work function metal layer and the spacer.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A barrier layer is formed in a first region and a second region of a semiconductor substrate. The barrier layer formed in the first region is thinned before a step of forming a first work function layer on the barrier layer. The first work function layer formed on the first region is then removed. The process of thinning the barrier layer in the first region and the process of removing the first work function layer in the first region are performed separately for ensuring the coverage of the first work function layer in the second region. The electrical performance of the semiconductor device and the uniformity of the electrical performance of the semiconductor device may be improved accordingly.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A barrier layer is formed in a first region and a second region of a semiconductor substrate. The barrier layer formed in the first region is thinned before a step of forming a first work function layer on the barrier layer. The first work function layer formed on the first region is then removed. The process of thinning the barrier layer in the first region and the process of removing the first work function layer in the first region are performed separately for ensuring the coverage of the first work function layer in the second region. The electrical performance of the semiconductor device and the uniformity of the electrical performance of the semiconductor device may be improved accordingly.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a shallow trench isolation (STI) around the fin-shaped structure; forming a gate layer on the fin-shaped structure and the STI; removing part of the gate layer, part of the fin-shaped structure, and part of the STI to form a trench; and forming a dielectric layer into the trench to form a single diffusion break (SDB) structure.

Abstract: The present invention provides a method of fabricating a fin field effect transistor (finFET), comprising: firstly, an interfacial layer is formed on a fin structure, next, a high-k dielectric layer is formed on the interfacial layer; afterwards, a stress film is formed on the high-k dielectric layer, an annealing process is then performed to the stress film, and an etching process is performed to remove the stress film.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon and a shallow trench isolation (STI) around the fin-shaped structure, in which the fin-shaped structure has a top portion and a bottom portion; forming a first doped layer on the STI and the top portion; and performing a first anneal process.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon and a shallow trench isolation (STI) around the fin-shaped structure, in which the fin-shaped structure has a top portion and a bottom portion; forming a first doped layer on the STI and the top portion; and performing a first anneal process.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon and a shallow trench isolation (STI) around the fin-shaped structure, in which the fin-shaped structure has a top portion and a bottom portion; forming a first doped layer on the STI and the top portion; and performing a first anneal process.

Abstract: A method of forming a semiconductor device is disclosed. Provided is a substrate having at least one MOS device, at least one metal interconnection and at least one MOS device formed on a first surface thereof. A first anisotropic etching process is performed to remove a portion of the substrate from a second surface of the substrate and thereby form a plurality of vias in the substrate, wherein the second surface is opposite to the first surface. A second anisotropic etching process is performed to remove another portion of the substrate from the second surface of the substrate and thereby form a cavity in the substrate, wherein the remaining vias are located below the cavity. An isotropic etching process is performed to the cavity and the remaining vias.

Abstract: A method of forming a semiconductor device is disclosed. Provided is a substrate having at least one MOS device, at least one metal interconnection and at least one MOS device formed on a first surface thereof. A first anisotropic etching process is performed to remove a portion of the substrate from a second surface of the substrate and thereby form a plurality of vias in the substrate, wherein the second surface is opposite to the first surface. A second anisotropic etching process is performed to remove another portion of the substrate from the second surface of the substrate and thereby form a cavity in the substrate, wherein the remaining vias are located below the cavity. An isotropic etching process is performed to the cavity and the remaining vias.

Abstract: A non-volatile memory cell having a local silicon nitride layer to control dispersion of hot electrons is disclosed. The dual-bit non-volatile memory cell has a stack of layers including silicon on the surface of a substrate. The stack of layers has at least one first oxide silicon layer and a silicon nitride layer overlying the first oxide silicon layer. An opening is formed in the stack of layers and a gate oxide layer is deposited on the surface of the substrate within the opening. A control gate is formed on the gate oxide layer followed by a second oxide silicon layer overlying the surfaces of the control gate and the stack of layers. A second polysilicon layer is formed overlying the gate oxide layer. Dual split-gates are then formed on the second polysilicon layer.

Abstract: A non-volatile memory cell having a local silicon nitride layer to control dispersion of hot electrons is disclosed. The dual-bit non-volatile memory cell has a stack of layers including silicon on the surface of a substrate. The stack of layers has at least one first oxide silicon layer and a silicon nitride layer overlying the first oxide silicon layer. An opening is formed in the stack of layers and a gate oxide layer is deposited on the surface of the substrate within the opening. A control gate is formed on the gate oxide layer followed by a second oxide silicon layer overlying the surfaces of the control gate and the stack of layers. A second polysilicon layer is formed overlying the gate oxide layer. Dual split-gates are then formed on the second polysilicon layer.

Abstract: A non-volatile memory cell having a local silicon nitride layer to control dispersion of hot electrons is disclosed. The dual-bit non-volatile memory cell has a stack of layers including silicon on the surface of a substrate. The stack of layers has at least one first oxide silicon layer and a silicon nitride layer overlying the first oxide silicon layer. An opening is formed in the stack of layers and a gate oxide layer is deposited on the surface of the substrate within the opening. A control gate is formed on the gate oxide layer followed by a second oxide silicon layer overlying the surfaces of the control gate and the stack of layers. A second polysilicon layer is formed overlying the gate oxide layer. Dual split-gates are then formed on the second polysilicon layer.

Abstract: A non-volatile memory cell having a local silicon nitride layer to control dispersion of hot electrons is disclosed. The dual-bit non-volatile memory cell has a stack of layers including silicon on the surface of a substrate. The stack of layers has at least one first oxide silicon layer and a silicon nitride layer overlying the first oxide silicon layer. An opening is formed in the stack of layers and a gate oxide layer is deposited on the surface of the substrate within the opening. A control gate is formed on the gate oxide layer followed by a second oxide silicon layer overlying the surfaces of the control gate and the stack of layers. A second polysilicon layer is formed overlying the gate oxide layer. Dual split-gates are then formed on the second polysilicon layer.

Abstract: Steep spacer is formed by using depositing and etching of dual conformal layers. A first conformal dielectric layer is deposited on a substrate with a gate electrode structure formed thereon. Then, a second conformal layer is deposited on the first conformal dielectric layer. The second conformal layer is anisotropically etched to form a first spacer on the sidewall of the first conformal dielectric layer. Next, the first conformal layer is anisotropically etched by using the first spacer as a mask to form a second spacer on the sidewall of the gate electrode structure. Then, the first spacer is removed and the second spacer is steep.

Abstract: Steep spacer is formed by using depositing and etching of dual conformal layers. A first conformal dielectric layer is deposited on a substrate with a gate electrode structure formed thereon. Then, a second conformal layer is deposited on the first conformal dielectric layer. The second conformal layer is anisotropically etched to form a first spacer on the sidewall of the first conformal dielectric layer. Next, the first conformal layer is anisotropically etched by using the first spacer as a mask to form a second spacer on the sidewall of the gate electrode structure. Then, the first spacer is removed and the second spacer is steep.

Abstract: A method of fabricating a flash memory is disclosed: firstly, a P-type silicon substrate is divided into a PMOS area, an NMOS area, and a flash memory area. The first polysilicon layer and the first oxide layer are formed at the flash memory area. Thereafter, the second polysilicon layer, the second oxide layer, and a layer of TEOS are formed. The first photo resist is then formed to define the gate pattern of the flash cell array, and then a process of N+ ion implantation is performed to form the source and drain of the flash cell array. After stripping the first photo resist, the second photo resist is formed to define the gate pattern at the NMOS area, and a process of N+ ion implantation is performed to form the NLDD structure. After stripping the second photo resist, the first sidewall is formed, and then a process of N− ion implantation is performed to form the NMOS source/drain. The third photo resist is then formed to define the gate pattern at the PMOS area.

Abstract: A method of making dual-gate structure with only three masking steps is provided.