Abstract: A high temperature resistant insulating composition includes an organic polymer and an inorganic binder. The inorganic binder is ranged between 10% and 90% by weight of the high temperature resistant insulating composition. The high temperature resistant insulating composition still possesses strength and insulating property after a high temperature treatment.

Abstract: Packet processing system and method embodiments implemented in a peripheral component interconnect-express (PCIE) compliant system are disclosed. One method embodiment, among others, comprises receiving a packet having at least a first type of data and a second type of data over a PCIE connection, and segregating the entire packet into two contiguous groups, a first group comprising the first type of data and a second group comprising the second type of data.

Abstract: An assembled circuit comprising an inductive component, a connecting conductor, and a first electronic component is disclosed. The connecting conductor is adapted to wrap a first surface of the inductive component. The first electronic component stacks on the inductive component. The assembled circuit is electrically connected to the carrier via the connecting conductor.

Abstract: A method for fabricating a non-volatile memory is provided. Parallel-arranged isolation structures are disposed in a substrate and protrude from the surface of the substrate to define active regions. Mask layers intersecting the isolation structures are deposited on the substrate. The surface of the mask layers is higher than that of the isolation structures. Doped regions are formed in the substrate. Insulating layers are deposited on the substrate between the mask layers. The insulating layers and the mask layers have different etch selectivities. The mask layers are removed to expose the substrate. A tunneling dielectric layer is formed on the substrate. A floating gate is deposited on the substrate surrounded by the isolation structures and the insulating layers. The surface of the floating gate is lower than that of the isolation structures. An inter-gate dielectric layer is deposited on the substrate. A control gate is disposed between the insulating layers.

Abstract: The present disclosure provides system and method embodiments for synchronizing access to memory between a plurality of modules in a pipelined system. One system embodiment, among others, includes an upstream module and a downstream module that each share one or more locations in memory. The upstream module is configured to receive a command pair having matched identifiers, one half (wait command) of which enables the upstream module to delay access to the memory to avoid read-after-write (RAW) hazard, the other half (signal command) which is passed to the downstream module. The downstream module passes the identifier from the signal command to the upstream module at a time corresponding to the downstream module reaching an idle state, thus ceasing access to the memory. The upstream module, upon determining that the identifier received over a direct connection from the downstream module is from the command pair, accesses the one or more locations in the memory.

Abstract: A quasi-axial optical imagery projection system is disclosed in this paper. The system includes optical imagery sets; each may be lenses, mirrors, or a combination of both. The system also has a light source close to an imager, which may be a planar mask with a pattern, a LCD imager, or other suitable imagers. The system also has a display screen. Both the imager and the display screen are set at acute angles with respect to an optical axis so that what is projected on the display screen is a magnified image of the imager by a magnification factor that has a transverse component and a longitudinal component. This quasi-axial projection system may be made thinner than other rear projection system of comparable screen size.

Abstract: The present disclosure provides system and method embodiments for synchronizing access to memory between a plurality of modules in a pipelined system. One system embodiment, among others, includes an upstream module and a downstream module that each share one or more locations in memory. The upstream module is configured to receive a command pair having matched identifiers, one half (wait command) of which enables the upstream module to delay access to the memory to avoid read-after-write (RAW) hazard, the other half (signal command) which is passed to the downstream module. The downstream module passes the identifier from the signal command to the upstream module at a time corresponding to the downstream module reaching an idle state, thus ceasing access to the memory. The upstream module, upon determining that the identifier received over a direct connection from the downstream module is from the command pair, accesses the one or more locations in the memory.

Abstract: Multiple graphics processor system and method embodiments are disclosed. One system embodiment, among others, comprises a multiple graphics processor system, comprising a first graphics processing unit having first status information and a second graphics processing unit having second status information, and first key logic corresponding to the first graphics processing unit, the first key logic configured to compare the first and second status information and communicate to the first graphics processing unit a key corresponding to the lowest completed stage of processing among the first and second graphics processing units.

Abstract: Packet processing system and method embodiments implemented in a peripheral component interconnect-express (PCIE) compliant system are disclosed. One method embodiment, among others, comprises receiving a packet having at least a first type of data and a second type of data over a PCIE connection, and segregating the entire packet into two contiguous groups, a first group comprising the first type of data and a second group comprising the second type of data.

Abstract: The present invention discloses an IP address construction and lookup method and apparatus used in routers, which uses a compress technology to reduce memory size occupied by a segment array and a plurality of next hop arrays used in an indirect lookup table method, and also reduce the number of memory accesses from 1 to 4 times. Besides, only one memory access is required if a pipeline scheme is in use. In addition, when the routing table is updating, it is unnecessary to rebuild the forwarding table and capable of finishing newer actions.

Abstract: Disclosed is a stator structure of a rotary device and its forming method. The method for forming a stator structure includes the steps of (a) forming a first part having a first middle portion with a through hole, and M pieces of extending portions extending from the first middle portion, (b) forming a second part having a second middle portion with a through hole, and N pieces of extending portions extending from the second middle portion, (c) alternately bending the M pieces of extending portions of the first part toward a first direction and alternately bending the N pieces of extending portions of the second part toward a second direction opposite to the first directon, respectively, and (d) correspondingly combining the first and second parts together to form the stator structure in which the bent extending portions of the first and second parts constitute a columnar portion of the stator structure for winding a coil thereon, wherein M and N are even numbers not less than four, respectively.

Abstract: The present invention relates to a nucleic acid kit for bacterial pathogen diagnosis and method for using the same, which provides with a quick diagnosis for 20 species of bacterial pathogens. The present invention is to align the nucleic acid sequences of each bacterial pathogen, single out the specific region thereof, find out the corresponsive consensus primers, and amplify the specific nucleic acid sequences of each bacterial pathogen, whereafter the nucleic acid kit is acquired. Further, such nucleic acid kit can be utilized as probes to be conjugated on polymers as diagnostic chips for bacterial pathogens (for example, the meningitis chip), and then the detection reaction proceeds as the nucleic acid sequences of pathogen purified from clinical sample and amplified by using the foregoing primers are to react with the bacterial pathogen diagnostic chip of the present invention, with the species of the infecting bacteria thus being determined.

Abstract: The present invention discloses an IP address construction and lookup method and apparatus used in routers, which uses a compress technology to reduce memory size occupied by a segment array and a plurality of next hop arrays used in an indirect lookup table method, and also reduce the number of memory accesses from 1 to 4 times. Besides, only one memory access is required if a pipeline scheme is in use. In addition, when the routing table is updating, it is unnecessary to rebuild the forwarding table and capable of finishing newer actions.

Abstract: A circuit breaker has a body providing a lever pivotally mounted on the upper end thereof. Two terminals are disposed within the body, wherein the first terminal forms a bimetal thereon. The terminals are electrically connected with each other in a normal state. A linkage is mounted on an end of the lever, which forms an isolated member on the lower end of the linkage. Pressing the lever, the isolated member of the linkage will moved upwards to separate the two terminals. When the lever is held by some heavy substances, the bimetal can be deformed to disconnect with the second terminal in over-current for cutting out the circuit.