Abstract: A semiconductor package having a low profile is disclosed. In embodiments, a surface mounted component may be mounted directly to the core of the semiconductor package substrate, so that there is no conductive layer, plating layers or solder paste between the component and the substrate core. The surface mounted component may be any type of component which may be surface mounted on a substrate according to an SMT process, including for example passive components and various packaged semiconductors.

Abstract: A method is disclosed for forming semiconductor packages by a process of punching and cutting the packages from a panel of integrated circuits. During an encapsulation process for encapsulating the packages in a molding compound, portions of the panel may be left free of molding compound. Portions of the panel left free of molding compound may subsequently be punched from the panel. These punched areas may define chamfers, notches or a variety of other curvilinear, rectilinear or irregular shapes in the outer edges of the finished semiconductor package. After the panel is punched, the integrated circuits may be singulated. By punching areas from the panel, and then cutting along straight edges, a simple, effective and cost efficient method is disclosed for obtaining finished semiconductor packages of a variety of desired shapes.

Abstract: A dummy circuit pattern is disclosed on a surface of a substrate for a semiconductor package, the dummy circuit pattern including straight line segments having a length controlled so as not to generate stresses within the line segments above a desired stress. The dummy circuit pattern may be formed of lines, or contiguous or spaced polygons, such as hexagons. Portions of the dummy circuit pattern may also be formed with an orientation, size and position that are randomly selected.

Abstract: A dummy circuit pattern is disclosed on a surface of a substrate for a semiconductor package, the dummy circuit pattern including straight line segments having a length controlled so as not to generate stresses within the line segments above a desired stress. The dummy circuit pattern may be formed of lines, or contiguous or spaced polygons, such as hexagons. Portions of the dummy circuit pattern may also be formed with an orientation, size and position that are randomly selected.

Abstract: Improved techniques for stacking integrated circuit dies within an integrated circuit package are disclosed. These improved techniques allow greater stacking density of integrated circuit dies within an integrated circuit package. Additionally, the improved stacking techniques permit conventional bonding techniques for electrical connection of the various integrated circuit dies to each other or to a substrate. These improved approaches are particularly useful for stacking same size (and often same function) integrated circuit dies within integrated circuit packages. One example of such an integrated circuit package is a non-volatile memory integrated circuit package that contains multiple, like-sized memory storage integrated circuit dies arranged in a stack.

Abstract: A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package.

Abstract: An intregrated circuit package, which has an intregrated circuit die thereto, is mounted to a system board. The ground trace of the system board is connected to the package, which has a pluality of ground leads on its surface. An electrically conductive epoxy is placed on the ground leads and adheres the package lid to the package board and ground the package lid. A heat sink is mounted to the package lid with an electrically conductive adhesive or electrically conductive slips that extend from a flange of the package lid to a flange of the heat sink to ground the heat sink.

Abstract: A flip chip package compatible with first and second die footprints includes an interconnection substrate having a connection surface configured to receive an integrated circuit die that has either a first or a second die footprint. The interconnection substrate has a plurality of conductive pads on its connection surface for establishing a connection to the conductive pads of the selected integrated circuit die. The connection surface conductive pads have a first section corresponding to the conductive pads of an integrated circuit with a first die footprint. It also has a second section corresponding to the conductive pads of an integrated circuit with a second die footprint. The first and second sections of conductive pads overlap, reducing the size of the package footprint while allowing the same package to be used with different integrated circuit dies.