Patents by Inventor Shrinivas KUDEKAR

Shrinivas KUDEKAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10511328
    Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to an efficient list decoder for list decoding low density parity check (LDPC) codes.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: December 17, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Shrinivas Kudekar, Thomas Joseph Richardson, Gabi Sarkis, Vincent Loncke
  • Publication number: 20190363828
    Abstract: Aspects of the disclosure relate to polar coding. A polar codeword may be generated by sorting a plurality of synthetic channels utilized for transmission of the polar codeword over an air interface in order of reliability utilizing a convex combination of the mutual information calculated for each synthetic channel based on an Additive White Gaussian Noise (AWGN) channel and the mutual information calculated for each synthetic channel based on a binary erasure channel. A polar codeword may further be generated by sorting the plurality of synthetic channels in order of reliability utilizing cumulative sums calculated for each synthetic channel. Each cumulative sum may be calculated from a binary representation of a position of the synthetic channel within the plurality of synthetic channels.
    Type: Application
    Filed: August 9, 2019
    Publication date: November 28, 2019
    Inventors: Shrinivas KUDEKAR, Gabi SARKIS, Thomas RICHARDSON
  • Publication number: 20190356337
    Abstract: Certain aspects of the present disclosure generally relate to techniques for enhanced puncturing and low-density parity-check (LDPC) code structure. A method for wireless communications by a transmitting device is provided. The method generally includes encoding a set of information bits based on a LDPC code to produce a code word, the LDPC code defined by a base matrix having a first number of variable nodes and a second number of check nodes; puncturing the code word according to a puncturing pattern designed to puncture bits corresponding to at least two of the variable nodes to produce a punctured code word; adding at least one additional parity bit for the at least two punctured variable nodes; and transmitting the punctured code word.
    Type: Application
    Filed: July 29, 2019
    Publication date: November 21, 2019
    Inventors: Thomas Joseph RICHARDSON, Shrinivas KUDEKAR
  • Patent number: 10469104
    Abstract: Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method for wireless communications by a transmitting device is provided.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: November 5, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Shrinivas Kudekar, Thomas Joseph Richardson
  • Patent number: 10454499
    Abstract: Certain aspects of the present disclosure generally relate to techniques for enhanced puncturing and low-density parity-check (LDPC) code structure. A method for wireless communications by a transmitting device is provided. The method generally includes encoding a set of information bits based on a LDPC code to produce a code word, the LDPC code defined by a base matrix having a first number of variable nodes and a second number of check nodes; puncturing the code word according to a puncturing pattern designed to puncture bits corresponding to at least two of the variable nodes to produce a punctured code word; adding at least one additional parity bit for the at least two punctured variable nodes; and transmitting the punctured code word.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: October 22, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Joseph Richardson, Shrinivas Kudekar
  • Patent number: 10419176
    Abstract: Various aspects of the present disclosure provide for methods, apparatus, and computer software for transmitting in-band control information in a wireless communication channel. A control and data information coding scheme is utilized to reduce the block error rate (BLER) of in-band control information in various scenarios. A subframe carries coded control information, coded data information, and coded control-data information for reducing the BLER of the in-band control information. The coded control information and coded data information are mix-coded to generate coded control-data information.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: September 17, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Saurabha Tavildar, Thomas Richardson, Shrinivas Kudekar
  • Patent number: 10419027
    Abstract: Certain aspects of the present disclosure generally relate to techniques for efficient, high-performance decoding of low-density parity check (LDPC) codes, for example, by using an adjusted minimum-sum (AdjMS) algorithm, which involves approximating an update function and determining magnitudes of outgoing log likelihood ratios (LLRs). Similar techniques may also be used for decoding turbo codes. Other aspects, embodiments, and features (such as encoding technique) are also claimed and described.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: September 17, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Joseph Richardson, Shrinivas Kudekar, Vincent Loncke
  • Publication number: 20190280817
    Abstract: Certain aspects of the present disclosure relate to techniques and apparatus for improving decoding latency and performance of Polar codes. An exemplary method generally includes generating a codeword by encoding information bits, using a multi-dimensional interpretation of a polar code of length N, determining, based on one or more criteria, a plurality of locations within the codeword to insert error correction codes generating the error correction codes based on corresponding portions of the information bits, inserting the error correction codes at the determined plurality of locations, and transmitting the codeword. Other aspects, embodiments, and features are also claimed and described.
    Type: Application
    Filed: May 24, 2019
    Publication date: September 12, 2019
    Inventors: Shrinivas KUDEKAR, Thomas Joseph RICHARDSON
  • Publication number: 20190245654
    Abstract: Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARQ) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity.
    Type: Application
    Filed: April 17, 2019
    Publication date: August 8, 2019
    Inventors: Thomas Joseph RICHARDSON, Shrinivas KUDEKAR
  • Patent number: 10348451
    Abstract: Certain aspects of the present disclosure relate to techniques and apparatus for improving decoding latency and performance of Polar codes. An exemplary method generally includes generating a codeword by encoding information bits, using a multi-dimensional interpretation of a polar code of length N, determining, based on one or more criteria, a plurality of locations within the codeword to insert error correction codes generating the error correction codes based on corresponding portions of the information bits, inserting the error correction codes at the determined plurality of locations, and transmitting the codeword. Other aspects, embodiments, and features are also claimed and described.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: July 9, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Shrinivas Kudekar, Thomas Richardson
  • Patent number: 10348329
    Abstract: Aspects of the present disclosure relate to low density parity check (LDPC) coding utilizing a configurable circular buffer for rate matched transmissions. The circular buffer may be configured based on a selected mother code rate and a fixed circular buffer length. For example, the respective sizes of the systematic and parity bit sections of the circular buffer may be variable based on the selected mother code rate.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: July 9, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Joseph Binamira Soriaga, Shrinivas Kudekar, Thomas Joseph Richardson, Jing Jiang, Renqiu Wang
  • Patent number: 10340949
    Abstract: Aspects of the present disclosure relate to low density parity check (LDPC) coding utilizing LDPC base graphs. Two or more LDPC base graphs may be maintained that are associated with different ranges of overlapping information block lengths. A particular LDPC base graph may be selected for an information block based on the information block length of the information block. Additional metrics that may be considered when selecting the LDPC base graph may include the code rate utilized to encode the information block and/or the lift size applied to each LDPC base graph to produce the information block length of the information block.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: July 2, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Joseph Binamira Soriaga, Gabi Sarkis, Shrinivas Kudekar, Thomas Richardson, Vincent Loncke
  • Publication number: 20190199475
    Abstract: Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARQ) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity.
    Type: Application
    Filed: February 28, 2019
    Publication date: June 27, 2019
    Inventors: Thomas Joseph RICHARDSON, Shrinivas KUDEKAR
  • Patent number: 10312939
    Abstract: Certain aspects of the present disclosure provide low-density parity-check (LDPC) codes having pairwise orthogonality of adjacent rows, and a new decoder that exploits the pairwise row orthogonality for flexible decoder scheduling without performance loss. An apparatus includes a receiver configured to receive a codeword in accordance with a radio technology across a wireless channel via one or more antenna elements situated proximal the receiver. The apparatus includes at least one processor coupled with a memory and comprising decoder circuitry configured to decode the codeword based on a LDPC code to produce a set of information bits. The LDPC code is stored in the memory and defined by a base matrix having columns in which all adjacent rows are orthogonal in a last portion of the rows.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: June 4, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Richardson, Joseph Binamira Soriaga, Shrinivas Kudekar, Gabi Sarkis
  • Patent number: 10291354
    Abstract: Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARQ) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: May 14, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Joseph Richardson, Shrinivas Kudekar
  • Publication number: 20190052400
    Abstract: Methods, systems, and devices for wireless communication are described. In some examples, a wireless device (e.g., a user equipment (UE) or a base station) may encode a codeword from a set of information bits using an LDPC code. The wireless device may then transmit multiple versions of the codeword to improve the chances of the codeword being received. In some aspects, the wireless device may use the techniques herein to generate self-decodable redundancy versions of the codeword to be transmitted to the receiving device. Accordingly, a receiving device may be able to identify information bits from one or more redundancy versions of the codeword even if the receiving device failed to receive an original transmission of the codeword.
    Type: Application
    Filed: August 8, 2018
    Publication date: February 14, 2019
    Inventors: Joseph Binamira Soriaga, Shrinivas Kudekar, Thomas Joseph Richardson, Gabi Sarkis, Jing Jiang
  • Publication number: 20190044540
    Abstract: A wireless device (e.g., a base station or user equipment (UE)) may encode a codeword using a polar code for transmission over a wireless channel. The device may identify a set of bit locations of the polar code for a set of information bits based on a bit index reliability sequence. The bit index reliability sequence may be based on applying an ordered combination of a universal partial order, an analytical method, and a simulation. The bit index reliability sequence may be determined based on a binary bit weighting for the set of bit channels that applies one or more weighting factors. In some cases, the device may store the bit index reliability sequence in a lookup table for encoding, decoding, or both. A device receiving the transmitted codeword may similarly utilize the bit index reliability sequence to decode the codeword and determine the transmitted information bits.
    Type: Application
    Filed: July 31, 2018
    Publication date: February 7, 2019
    Inventors: Jing Jiang, Gabi Sarkis, Yang Yang, Peter Gaal, Joseph Binamira Soriaga, Shrinivas Kudekar
  • Publication number: 20180367245
    Abstract: The present disclosure provides self-decodable redundancy versions for a systematic code. An apparatus for wireless communications includes at least one processor coupled with a memory and comprising encoder circuitry configured to encode a set of information bits using a systematic code to generate an encoded bit stream with information bits and parity bits, and bit ordering circuitry configured to re-order bits in the encoded bit stream to distribute the information bits and the parity bits. The apparatus includes a transmitter configured to transmit the re-ordered bits in accordance with a radio technology via one or more antenna elements situated proximate the receiver.
    Type: Application
    Filed: June 18, 2018
    Publication date: December 20, 2018
    Inventors: Joseph Binamira SORIAGA, Shrinivas KUDEKAR, Thomas RICHARDSON, Gabi SARKIS, Hari SANKAR, Jing JIANG
  • Patent number: 10157161
    Abstract: System, methods, and apparatus are described for transmitting encoded bits over a bus by conditionally embedding dynamically shielded information. In an example, the apparatus transmits a first group of encoded bits over a bus, generates a second group of encoded bits to be transmitted over the bus, where a first subset of the second group of encoded bits are encoded to avoid crosstalk-inducing bit transitions on adjacent lines of the bus, and configures one or more encoded bits of a second subset of the second group of encoded bits to ensure that the second group of encoded bits includes parity information and/or clock information, while further ensuring that crosstalk-inducing bit transitions in the second group of encoded bits are avoided.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: December 18, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Urs Niesen, Shrinivas Kudekar
  • Publication number: 20180358984
    Abstract: Certain aspects of the present disclosure provide low-density parity-check (LDPC) codes having pairwise orthogonality of adjacent rows, and a new decoder that exploits the pairwise row orthogonality for flexible decoder scheduling without performance loss. An apparatus includes a receiver configured to receive a codeword in accordance with a radio technology across a wireless channel via one or more antenna elements situated proximal the receiver. The apparatus includes at least one processor coupled with a memory and comprising decoder circuitry configured to decode the codeword based on a LDPC code to produce a set of information bits. The LDPC code is stored in the memory and defined by a base matrix having columns in which all adjacent rows are orthogonal in a last portion of the rows.
    Type: Application
    Filed: June 7, 2018
    Publication date: December 13, 2018
    Inventors: Thomas RICHARDSON, Joseph Binamira SORIAGA, Shrinivas KUDEKAR, Gabi SARKIS