Patents by Inventor Shrinivas KUDEKAR

Shrinivas KUDEKAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180359714
    Abstract: An apparatus are provided for wireless communication at a base station with improved PBCH construction and decoding. The base station apparatus constructs a PBCH payload, wherein a bit location is selected for encoding a plurality of bits of the PBCH based on an estimated reliability for the corresponding bits location wherein the plurality of bits comprises frozen bits, unknown bits that are unknown to a user equipment, and potentially known bits that are potentially known by the user equipment. The apparatus transmits the PBCH payload in at least one of a plurality of SS blocks. A UE receiving the PBCH decodes the PBCH based on a successive decoding order. The successive decoding order may be based on an estimated reliability for the corresponding bits, e.g., in which potentially known bits are decoded prior to unknown bits.
    Type: Application
    Filed: March 20, 2018
    Publication date: December 13, 2018
    Inventors: Bilal SADIQ, Juergen CEZANNE, Shrinivas KUDEKAR, Navid ABEDINI, Muhammad Nazmul ISLAM
  • Publication number: 20180294917
    Abstract: Various aspects described herein relate to techniques for rate matching and interleaving in wireless communications (e.g., 5G NR). In an example, a method described herein includes encoding one or more information bits to generate a first codeblock, rate matching the first codeblock to generate a second codeblock, segmenting, using bit distribution, the second codeblock into one or more sub-blocks each having a plurality of bits. The method further includes interleaving the plurality of bits on each of the one or more sub-blocks, concatenating, using bit collection, the one or more sub-blocks to generate a third codeblock in response to the interleaving, and transmitting a signal using the third codeblock.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 11, 2018
    Inventors: Vincent Loncke, Raghunath Kalavai, Yi Cao, Thomas Richardson, Joseph Binamira Soriaga, Shrinivas Kudekar
  • Publication number: 20180234114
    Abstract: Aspects of the present disclosure relate to low density parity check (LDPC) coding utilizing a configurable circular buffer for rate matched transmissions. The circular buffer may be configured based on a selected mother code rate and a fixed circular buffer length. For example, the respective sizes of the systematic and parity bit sections of the circular buffer may be variable based on the selected mother code rate.
    Type: Application
    Filed: February 12, 2018
    Publication date: August 16, 2018
    Inventors: Joseph Binamira Soriaga, Shrinivas Kudekar, Thomas Joseph Richardson, Jing Jiang, Renqiu Wang
  • Publication number: 20180226989
    Abstract: Aspects of the present disclosure relate to low density parity check (LDPC) coding utilizing LDPC base graphs. Two or more LDPC base graphs may be maintained that are associated with different ranges of overlapping information block lengths. A particular LDPC base graph may be selected for an information block based on the information block length of the information block. Additional metrics that may be considered when selecting the LDPC base graph may include the code rate utilized to encode the information block and/or the lift size applied to each LDPC base graph to produce the information block length of the information block.
    Type: Application
    Filed: April 2, 2018
    Publication date: August 9, 2018
    Inventors: Joseph Binamira Soriaga, Gabi Sarkis, Shrinivas Kudekar, Thomas Richardson, Vincent Loncke
  • Publication number: 20180226988
    Abstract: Aspects of the present disclosure relate to low density parity check (LDPC) coding utilizing LDPC base graphs. Two or more LDPC base graphs may be maintained that are associated with different ranges of overlapping information block lengths. A particular LDPC base graph may be selected for an information block based on the information block length of the information block. Additional metrics that may be considered when selecting the LDPC base graph may include the code rate utilized to encode the information block and/or the lift size applied to each LDPC base graph to produce the information block length of the information block.
    Type: Application
    Filed: September 19, 2017
    Publication date: August 9, 2018
    Inventors: Joseph Binamira Soriaga, Gabi Sarkis, Shrinivas Kudekar, Thomas Richardson, Vincent Loncke
  • Publication number: 20180205496
    Abstract: Aspects of the disclosure relate to polar coding. A polar codeword may be generated by sorting a plurality of synthetic channels utilized for transmission of the polar codeword over an air interface in order of reliability utilizing a convex combination of the mutual information calculated for each synthetic channel based on an Additive White Gaussian Noise (AWGN) channel and the mutual information calculated for each synthetic channel based on a binary erasure channel. A polar codeword may further be generated by sorting the plurality of synthetic channels in order of reliability utilizing cumulative sums calculated for each synthetic channel. Each cumulative sum may be calculated from a binary representation of a position of the synthetic channel within the plurality of synthetic channels.
    Type: Application
    Filed: January 12, 2018
    Publication date: July 19, 2018
    Inventors: Shrinivas Kudekar, Gabi Sarkis, Thomas Richardson
  • Publication number: 20180205498
    Abstract: Certain aspects of the present disclosure relate to techniques and apparatus for improving decoding latency and performance of Polar codes. An exemplary method generally includes generating a codeword by encoding information bits, using a multi-dimensional interpretation of a polar code of length N, determining, based on one or more criteria, a plurality of locations within the codeword to insert error correction codes generating the error correction codes based on corresponding portions of the information bits, inserting the error correction codes at the determined plurality of locations, and transmitting the codeword. Other aspects, embodiments, and features are also claimed and described.
    Type: Application
    Filed: March 13, 2018
    Publication date: July 19, 2018
    Inventors: Shrinivas KUDEKAR, Thomas RICHARDSON
  • Patent number: 9984035
    Abstract: System, methods, and apparatus are described that facilitate transmission/reception of data over a multi-line parallel bus. In an example, the apparatus selects from a sequential series of data bits a plurality of data bits for transmission over a plurality of parallel bus lines. For each bus line of the plurality of parallel bus lines, the apparatus compares a state of a current data bit selected for transmission on a current bus line during a current clock cycle with one or more conditions related to the current bus line or at least one bus line adjacent to the current bus line, wherein the one or more conditions includes a state of two data bits respectively transmitted on two bus lines adjacent to the current bus line during a previous clock cycle, and determines whether to transmit the current data bit on the current bus line based on the comparison.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: May 29, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Shrinivas Kudekar, Urs Niesen
  • Publication number: 20180131391
    Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to an efficient list decoder for list decoding low density parity check (LDPC) codes.
    Type: Application
    Filed: November 2, 2017
    Publication date: May 10, 2018
    Inventors: Shrinivas KUDEKAR, Thomas Joseph RICHARDSON, Gabi SARKIS, Vincent LONCKE
  • Publication number: 20180109269
    Abstract: Certain aspects of the present disclosure generally relate to techniques for efficient, high-performance decoding of low-density parity check (LDPC) codes, for example, by using an adjusted minimum-sum (AdjMS) algorithm, which involves approximating an update function and determining magnitudes of outgoing log likelihood ratios (LLRs). Similar techniques may also be used for decoding turbo codes. Other aspects, embodiments, and features (such as encoding technique) are also claimed and described.
    Type: Application
    Filed: October 12, 2017
    Publication date: April 19, 2018
    Inventors: Thomas Joseph RICHARDSON, Shrinivas KUDEKAR, Vincent LONCKE
  • Patent number: 9917675
    Abstract: Certain aspects of the present disclosure relate to techniques and apparatus for improving decoding latency and performance of Polar codes. An exemplary method generally includes generating a codeword by encoding information bits, using a multi-dimensional interpretation of a polar code of length N, determining, based on one or more criteria, a plurality of locations within the codeword to insert error correction codes generating the error correction codes based on corresponding portions of the information bits, inserting the error correction codes at the determined plurality of locations, and transmitting the codeword. Other aspects, embodiments, and features are also claimed and described.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: March 13, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Shrinivas Kudekar, Thomas Joseph Richardson
  • Publication number: 20180035427
    Abstract: Aspects of the disclosure relate to a sidelink signal communication scheme that provides for rapid adaptation of the sidelink transmission based on feedback received during each transmission time interval (TTI). In this way, any lack of precision in interference measurements, or rapid changes in the amount of interference, which otherwise might cause a modulation and coding scheme (MCS) that was selected for the sidelink transmission to be unsuitable, may be adapted to improve the reliability of the transmission. Other aspects, embodiments, and features are also claimed and described.
    Type: Application
    Filed: December 29, 2016
    Publication date: February 1, 2018
    Inventors: Piyush Gupta, Shrinivas Kudekar, Junyi Li
  • Publication number: 20170359086
    Abstract: Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method for wireless communications by a transmitting device is provided.
    Type: Application
    Filed: June 13, 2017
    Publication date: December 14, 2017
    Inventors: Shrinivas KUDEKAR, Thomas Joseph RICHARDSON
  • Publication number: 20170359148
    Abstract: Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARQ) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity.
    Type: Application
    Filed: June 13, 2017
    Publication date: December 14, 2017
    Inventors: Thomas Joseph RICHARDSON, Shrinivas KUDEKAR
  • Publication number: 20170353271
    Abstract: Certain aspects of the present disclosure relate to techniques and apparatus for improving decoding latency and performance of Polar codes. An exemplary method generally includes generating a codeword by encoding information bits, using a multi-dimensional interpretation of a polar code of length N, determining, based on one or more criteria, a plurality of locations within the codeword to insert error correction codes generating the error correction codes based on corresponding portions of the information bits, inserting the error correction codes at the determined plurality of locations, and transmitting the codeword. Other aspects, embodiments, and features are also claimed and described.
    Type: Application
    Filed: December 30, 2016
    Publication date: December 7, 2017
    Inventors: Shrinivas KUDEKAR, Thomas Joseph RICHARDSON
  • Publication number: 20170353267
    Abstract: Certain aspects of the present disclosure relate to techniques and apparatus for improving decoding latency and performance of Polar codes. An exemplary method generally includes generating a codeword by encoding information bits using a first code of length K to obtain bits for transmission via K channels, wherein the first code comprises a polar code, further encoding the bits in each of the K channels using a second code of length M, and transmitting the codeword.
    Type: Application
    Filed: December 30, 2016
    Publication date: December 7, 2017
    Inventors: Shrinivas KUDEKAR, Thomas Joseph RICHARDSON
  • Publication number: 20170331497
    Abstract: Certain aspects of the present disclosure generally relate to techniques for enhanced puncturing and low-density parity-check (LDPC) code structure. A method for wireless communications by a transmitting device is provided. The method generally includes encoding a set of information bits based on a LDPC code to produce a code word, the LDPC code defined by a base matrix having a first number of variable nodes and a second number of check nodes; puncturing the code word according to a puncturing pattern designed to puncture bits corresponding to at least two of the variable nodes to produce a punctured code word; adding at least one additional parity bit for the at least two punctured variable nodes; and transmitting the punctured code word.
    Type: Application
    Filed: May 11, 2017
    Publication date: November 16, 2017
    Inventors: Thomas Joseph RICHARDSON, Shrinivas KUDEKAR
  • Publication number: 20170331494
    Abstract: Techniques and apparatus are provided for efficiently generating multiple lifted low-density parity-check (LDPC) codes for a range of block lengths and having good performance. A method for wireless communications by a transmitting device generally includes selecting integer lifting values for a first lifting size value Z, selected from a range of lifting size values, wherein the selected integer lifting value is greater than a maximum lifting size value of the range of lifting size values; determining one or more integer lifting values for generating at least a second lifted LDPC code having a second lifting size value based on an operation involving the second lifting size value and the selected one or more integer lifting values for generating the first lifted LDPC code; encoding a set of information bits based on the second lifted LDPC to produce a code word; and transmitting the code word.
    Type: Application
    Filed: May 10, 2017
    Publication date: November 16, 2017
    Inventors: Thomas Joseph RICHARDSON, Shrinivas KUDEKAR
  • Publication number: 20170163375
    Abstract: System, methods, and apparatus are described that facilitate transmission/reception of data over a multi-line parallel bus. In an example, the apparatus transmits data bits over a parallel bus includes determining from a prior bus state, a plurality of free wires in the bus for a current bus state, where each free wire satisfies a crosstalk-avoidance constraint in the current bus state for all values of a bit transmitted on the free wire. The apparatus may encode a plurality of data bits using a crosstalk avoidance encoder to obtain a CAC-encoded word, compute an error detection or correction code for the CAC-encoded word, assign bits of the error detection or correction code to the plurality of free wires for transmission during the current bus state, and assign the CAC-encoded word to unassigned wires of the bus for transmission during the current bus state.
    Type: Application
    Filed: December 3, 2015
    Publication date: June 8, 2017
    Inventors: Urs Niesen, Shrinivas Kudekar
  • Publication number: 20170141895
    Abstract: Various aspects of the present disclosure provide for methods, apparatus, and computer software for transmitting in-band control information in a wireless communication channel. A control and data information coding scheme is utilized to reduce the block error rate (BLER) of in-band control information in various scenarios. A subframe carries coded control information, coded data information, and coded control-data information for reducing the BLER of the in-band control information. The coded control information and coded data information are mix-coded to generate coded control-data information.
    Type: Application
    Filed: June 2, 2016
    Publication date: May 18, 2017
    Inventors: Saurabha Tavildar, Thomas Richardson, Shrinivas Kudekar