Abstract: The present invention discloses a method that includes: providing two wafers; forming raised contacts on the two wafers; aligning the two wafers; bringing together the raised contacts; locally deflecting the two wafers; and bonding the raised contacts. The present invention also discloses a bonded-wafer structure that includes: a first wafer, the first wafer being locally deflected, the first wafer including a first raised contact; and a second wafer, the second wafer being locally deflected, the second wafer including a second raised contact, wherein the second raised contact is bonded to the first raised contact.

Abstract: The present invention discloses a method that includes: providing two wafers; forming raised contacts on the two wafers; aligning the two wafers; bringing together the raised contacts; locally deflecting the two wafers; and bonding the raised contacts. The present invention also discloses a bonded-wafer structure that includes: a first wafer, the first wafer being locally deflected, the first wafer including a first raised contact; and a second wafer, the second wafer being locally deflected, the second wafer including a second raised contact, wherein the second raised contact is bonded to the first raised contact.

Abstract: The present invention discloses a method that includes: providing two wafers; forming raised contacts on the two wafers; aligning the two wafers; bringing together the raised contacts; locally deflecting the two wafers; and bonding the raised contacts. The present invention also discloses a bonded-wafer structure that includes: a first wafer, the first wafer being locally deflected, the first wafer including a first raised contact; and a second wafer, the second wafer being locally deflected, the second wafer including a second raised contact, wherein the second raised contact is bonded to the first raised contact.

Abstract: Embodiments of a method of fabricating a substrate including thermally conductive structures, as well as devices made from such a substrate, are disclosed. Each thermally conductive structure includes a via and a number of carbon nanotubes formed within the via. An active circuit element disposed on the substrate may at least partially overlie (or underlie) a location of one of the vias. The substrate may be cut into a number of separate die, each die including some of the thermally conductive structures. Other embodiments are described and claimed.

Abstract: As embodiment of the invention relates to a device for performing NMR or ESR analysis. The device comprises a detection unit, a magnet, and a disk having a magnetic pattern. The detection unit comprises a sample holding space for holding a sample and a microcoil for detecting NMR or ESR signals generated within the sample. The magnet generates a static magnetic field within the sample. The disk and magnetic pattern, when rotating, generate an excitation magnetic field, which, together with the static magnetic field, creates an NMR or ESR within the sample. Other embodiments of the invention encompass methods for performing NMR or ESR analysis using the device and methods of making such devices.

Abstract: In one embodiment, the present invention includes a hybrid device having a first die including a semiconductor device and a second die coupled to the first die, where the second die includes a magnetic structure. The first die may be a semiconductor substrate, while the second die may be a magnetic substrate, and the first die may be stacked on the second die, in one embodiment. Other embodiments are described and claimed.

Abstract: An embodiment if the invention relates to an integrated on-chip NMR or ESR device for performing chemical analysis and medical diagnostics. Specifically, the device contains, on a single substrate, a sample holding space, a magnet for generating a static magnetic field across the sample holding space and a microcoil for generating an excitation magnetic field across sample holding space. The magnetic fields are able to create NMR or ESR within a sample in the sample holding space and collect and/or process the signals from the NMR or ESR. The substrate may comprise an array of microcoils and sample holding spaces for performing multiple NMR or ESR analysis, such as multiple DNA analysis. Other embodiments of the invention relate methods for fabricating such devices and methods for performing NMR or ESR analysis using such devices.

Abstract: A method for wafer stacking employing substantially uniform copper structures is described herein.

Abstract: An embodiment of the invention relates to a device comprising an array of optical magnetometers. The magnetometers comprise se a light source, a container having a chamber filled with an atomic vapor, and a photo detector capable of detecting optical properties of the atomic vapor. The substrate and the array of the magnetometers are designed such that the magnetometers are able to detect weak magnetic fields. Also, the magnetometers are capable of detecting distinct portions of a magnetic field, such as a non-uniform magnetic field, using a single or a plurality of the magnetometers in the array simultaneously. Other embodiment of the invention include methods of making a device that comprises an array of magnetometers and methods of detecting a magnetic field using the device. The device and method can be used in medical diagnostics, such as detecting biomagnetic activities of the human's heart and brain.

Abstract: An embodiment of the invention relates to an integrated on-chip NMR or ESR device for performing chemical analysis and medical diagnostics. Specifically, the device contains, on a single substrate, a sample holding space, a magnet for generating a static magnetic field across the sample holding space and a microcoil for generating an excitation magnetic field across sample holding space. The magnetic fields are able to create NMR or ESR within a sample in the sample holding space and collect and/or process the signals from the NMR or ESR. The substrate may comprise an array of microcoils and sample holding spaces for performing multiple NMR or ESR analysis, such as multiple DNA analysis. Other embodiments of the invention relate methods for fabrication such devices and methods for performing NMR or ESR analysis using such devices.

Abstract: An embodiment of the invention relates to a portable or handheld device for performing NMR analysis. The device comprises a console and a strip which can be placed into the console through a slot or other means. The strip comprises a sample holding place and a microcoil for generating an excitation magnetic field across a sample in the sample holding space. A permanent magnet is provided either by the console or the strip and generates a static magnetic field which, together with the excitation field, creates NMR within the sample. Other embodiments of the invention also encompass method of performing NMR analysis using the portable device and method of making such devices.

Abstract: Embodiments of the invention relate to device, method, and system for separation and/or detection of biological cells and biomolecules using micro-channels, magnetic interactions, and magnetic tunnel junctions. The micro-channels can be integrated into a microfluidic device that may be part of an integrated circuit. Magnetic interactions used for the separation are created, in part, by magnetic stripes associated with the micro-channels. Detection of biological cells and biomolecules is effectuated by a magnetic tunnel junction sensor that comprises two ferromagnetic layers separated by a thin insulating layer. The magnetic tunnel junction sensor can be integrated into a silicon based device, such a microfluidic device, an integrated circuit, or a microarray to achieve rapid and specific separation and/or detection of biomolecules and cells.

Abstract: Backside connections for 3D integrated circuits and methods to fabricate thereof are described. A stack of a first wafer over a second wafer that has a substrate of the first wafer on top of the stack, is formed. The substrate of the first wafer is thinned. A first dielectric layer is deposited on the thinned substrate. First vias extending through the substrate to the first wafer are formed in the first dielectric layer. A conductive layer is deposited in the first vias and on the first dielectric layer to form thick conductive lines. Second dielectric layer is formed on the conductive layer. Second vias extending to the conductive lines are formed in the second dielectric layer. Conductive bumps extending into the second vias and offsetting the first vias are formed on the second dielectric layer.

Abstract: The invention provides a stacked wafer structure with decreased failures. In one embodiment, there is a barrier layer deposited on exposed surfaces of conductors that extend across a distance between first and second device structures. The barrier layer may prevent diffusion and electromigration of the conductor material, which may decrease incidences of shorts and voids in the stacked wafer structure.

Abstract: An embodiment of the present invention is a technique to provide heat extraction for semiconductor devices. At least a thermoelectric film is fabricated onto a bare wafer. The backside of the bare wafer is bonded to an active wafer having at least a device. The bonded bare and active wafers are annealed.

Abstract: Some embodiments of the present invention include apparatuses and methods relating to stacked wafer or die packaging with enhanced thermal and device performance.

Abstract: A method of fabricating a microelectronic package having a direct contact heat spreader, a package formed according to the method, a die-heat spreader combination formed according to the method, and a system incorporating the package. The method comprises metallizing a backside of a microelectronic die to form a heat spreader body directly contacting and fixed to the backside of the die thus yielding a die-heat spreader combination. The package includes the die-heat spreader combination and a substrate bonded to the die.

Abstract: A method of bonding semiconductor devices is disclosed. The method comprises providing a first substrate having a first conductive interconnecting structure formed thereon and a second substrate having a second conductive interconnecting structure formed thereon. A first conductive passivation layer is selectively formed over exposed areas of the first conductive interconnecting structure. A second conductive passivation layer is selectively formed over exposed areas of the second conductive interconnecting structure. The first substrate and the second substrate are bonded together in such a way that the first conductive passivation layer bonds to the second conductive passivation layer to create a passivation-passivation interface.

Abstract: A controlled collapse chip connection (C4) comprises a copper metal C4 bump formed on an integrated circuit substrate, where the C4 bump includes a metal barrier cap to prevent electromigration of the copper metal. The barrier cap is formed from nickel or cobalt and it can either be formed on a top surface of the C4 bump or it can encapsulate the C4 bump. A method of forming the C4 bump with the barrier cap comprises providing an integrated circuit substrate, depositing a photoresist layer on a top surface of the integrated circuit substrate, exposing and developing the photoresist layer to form an opening, depositing copper metal into the opening to form a C4 bump, plating a metal barrier layer onto a surface of the C4 bump, and stripping the photoresist layer.

Abstract: A method comprising: coating a conductive bump on a first substrate with a conductive material to form a coated conductive bump; coating a conductive bump on a second substrate with a conductive material to form a coated conductive bump; and bonding the coated conductive bump on the first substrate to the coated conductive bump on the second substrate to electrically connect the first substrate to the second substrate.