Abstract: Numerous embodiments of a stacked device underfill and a method of formation are disclosed. In one embodiment, a method of forming stacked semiconductor device with an underfill comprises forming one or more layers of compliant material on at least a portion of the top surface of a substrate, said substrate, curing at least a portion of the semiconductor device, selectively removing a portion of the one or more layers of compliant material, and assembling the substrate into a stacked semiconductor device.

Abstract: Embodiments of a method and apparatus for bonding wafers are disclosed. The bonded wafers may include self-passivating interconnects. Other embodiments are described and claimed.

Abstract: Using imaging techniques to determine if stacked wafers are in proper alignment. An infrared radiation source and an infrared camera are positioned on opposing sides of a stacked wafer. The infrared radiation source emits infrared radiation that penetrates and passes through the stacked wafer. The infrared radiation is then captured by the infrared camera. Fiducial marks that were previously patterned on each wafer of the stack are exposed in an image produced by the captured infrared radiation. The degree of alignment of the wafers can be measured using the fiducial marks exposed in the image.

Abstract: Embodiments include electronic assemblies and methods for forming electronic assemblies. Certain methods include forming a thermoelectric cooling (TEC) structure on a die, the TEC structure including a plurality of spaced apart TEC legs. A polymer is positioned between the spaced apart TEC legs of the TEC structure. The TEC structure may be positioned between the die and the heat spreader. In one method, a polymer in solid form is positioned on the TEC legs. The polymer in solid form is heated to a temperature sufficient so that a liquid polymer is formed, and the liquid polymer flows between the TEC legs. After being positioned between the TEC legs, the liquid polymer is solidified. Other embodiments are described and claimed.

Abstract: Disclosed are various embodiments of a method of forming vias for backside connections in a wafer stack, wherein the vias are formed by non-thermal laser ablation. Other embodiments are described an claimed.

Abstract: A method of forming self-passivating interconnects. At least one of two mating bond structures is formed, at least in part, from an alloy of a first metal and a second metal (or other element). The second metal is capable of migrating through the first metal to free surfaces of the mating bond structures. During bonding, the two mating bond structures are bonded together to form an interconnect, and the second metal segregates to free surfaces of this interconnect to form a passivation layer. Other embodiments are described and claimed.

Abstract: A method and apparatus for limiting net curvature in a substrate is provided. A layer is formed on one side of a substrate to limit curvature that may be introduced in the substrate by formation of a thermal spreading layer on an opposing side of the substrate. For example, introduction of a diamond layer on a substrate to dissipate thermal energy away from a semiconductor layer may introduce tensile or compressive stress in the substrate and result in undesirable bowing and/or warping of the substrate. To limit this curvature, a curvature limiting layer, e.g. another diamond layer, may be formed on subjacent to the substrate.

Abstract: A three-dimensional integrated circuit formed by applying a material to fill a gap between coupled wafers and slicing the coupled wafers into dice. A method for filling a gap between coupled wafers. Various embodiments include at least one of spinning a coupled wafer pair, drilling a hole into one of the coupled wafers, and using a vacuum to aid in the dispersion of the material.

Abstract: A method for wafer stacking employing substantially uniform copper structures is described herein.

Abstract: A microelectronic assembly is provided, having thermoelectric elements formed on a die so as to pump heat away from the die when current flows through the thermoelectric elements. In one embodiment, the thermoelectric elements are integrated between conductive interconnection elements on an active side of the die. In another embodiment, the thermoelectric elements are on a backside of the die and electrically connected to a carrier substrate on a front side of the die. In a further embodiment, the thermoelectric elements are formed on a secondary substrate and transferred to the die.

Abstract: Wafer stacking employing substantially uniform copper structures is described herein.

Abstract: A microelectronic assembly is provided, having thermoelectric elements formed on a die so as to pump heat away from the die when current flows through the thermoelectric elements. In one embodiment, the thermoelectric elements are integrated between conductive interconnection elements on an active side of the die. In another embodiment, the thermoelectric elements are on a backside of the die and electrically connected to a carrier substrate on a front side of the die. In a further embodiment, the thermoelectric elements are formed on a secondary substrate and transferred to the die.

Abstract: Disclosed are various embodiments of a method of forming vias for backside connections in a wafer stack, wherein the vias are formed by non-thermal laser ablation. Other embodiments are described an claimed.

Abstract: A three-dimensional integrated circuit formed by applying a material to fill a gap between coupled wafers and slicing the coupled wafers into dice. A method for filling a gap between coupled wafers. Various embodiments include at least one of spinning a coupled wafer pair, drilling a hole into one of the coupled wafers, and using a vacuum to aid in the dispersion of the material.

Abstract: Embodiments of the invention provide a first component with a compliant interconnect bonded to a second component with a land pad by a metal to metal bond. In some embodiments, the first component may be a microprocessor die and the second component a package substrate.

Abstract: Numerous embodiments of a stacked device filler and a method of formation are disclosed. In one embodiment, a method of forming a stacked device filler comprises forming a material layer between two or more substrates of a stacked device, and causing a reaction in at least a portion of the material, wherein the reaction may comprise polymerization, and the material layer may be one or a combination of materials, such as nonconductive polymer materials, for example.

Abstract: The present invention discloses a method that includes: providing two wafers; forming raised contacts on the two wafers; aligning the two wafers; bringing together the raised contacts; locally deflecting the two wafers; and bonding the raised contacts. The present invention also discloses a bonded-wafer structure that includes: a first wafer, the first wafer being locally deflected, the first wafer including a first raised contact; and a second wafer, the second wafer being locally deflected, the second wafer including a second raised contact, wherein the second raised contact is bonded to the first raised contact.

Abstract: The present invention discloses a method that includes: providing two wafers; forming raised contacts on the two wafers; aligning the two wafers; bringing together the raised contacts; locally deflecting the two wafers; and bonding the raised contacts. The present invention also discloses a bonded-wafer structure that includes: a first wafer, the first wafer being locally deflected, the first wafer including a first raised contact; and a second wafer, the second wafer being locally deflected, the second wafer including a second raised contact, wherein the second raised contact is bonded to the first raised contact.

Abstract: Apparatus and method of fabricating a heat dissipation device that includes at least one thermoelectric device fabricated with nano-wires for drawing heat from at least one high heat area on a microelectronic die. The nano-wires may be formed from bismuth containing materials and may be clustered of optimal performance.

Abstract: Wafer stacking employing substantially uniform copper structures is described herein.