Patents by Inventor Shu-Hao Chang

Shu-Hao Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9665007
    Abstract: An EUV collector is rotated between or during operations of an EUV photolithography system. Rotating the EUV collector causes contamination to distribute more evenly over the collector's surface. This reduces the rate at which the EUV photolithography system loses image fidelity with increasing contamination and thereby increases the collector lifetime. Rotating the collector during operation of the EUV photolithography system can induce convection and reduce the contamination rate. By rotating the collector at sufficient speed, some contaminating debris can be removed through the action of centrifugal force.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Chieh Chien, Shu-Hao Chang, Jui-Ching Wu, Tsung-Yu Chen, Tzu-Hsiang Chen, Ming-Chin Chien, Chia-Chen Chen, Jeng-Horng Chen
  • Patent number: 9607833
    Abstract: The method includes performing a photolithography process which includes using a photomask to pattern a radiation beam. The photolithography process also includes exposing a target substrate to the patterned radiation beam. During the exposing of the target surface, there is a real-time monitoring for particles incident or approximate the photomask.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: March 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Chieh Chien, Shu-Hao Chang, Hsiang-Yu Chou, Kuo-Chang Kau, Shun-Der Wu, Chia-Chen Chen, Jeng-Horng Chen
  • Publication number: 20170064595
    Abstract: A method of dynamic frequency selection includes receiving setting information of a WI-FI unit input by an input unit, controlling the WI-FI unit in a STA working mode to switch different channels to scan an available access point AP with dynamic frequency selection within one channel when receiving the setting information of setting the WI-FI unit to work in an AP working mode and the STA working mode simultaneously, controlling the WI-FI unit in the AP working mode to switch to the channel within which the WI-FI unit in the STA working mode scans the available access point AP when the WI-FI unit in the STA working mode scans the available access point AP, and controlling the WI-FI unit in the AP working mode to communicate with a terminal device via the switched access point AP.
    Type: Application
    Filed: October 26, 2015
    Publication date: March 2, 2017
    Inventor: SHU-HAO CHANG
  • Publication number: 20170060005
    Abstract: A lithography system includes a load lock chamber comprising an opening configured to receive a mask, an exposure module configured to expose a semiconductor wafer to a light source through use of the mask, and a cleaning module embedded inside the lithography tool, the cleaning module being configured to clean carbon particles from the mask.
    Type: Application
    Filed: August 31, 2015
    Publication date: March 2, 2017
    Inventors: Shu-Hao Chang, Norman Chen, Jeng-Horng Chen, Kuo-Chang Kau, Ming-Chin Chien, Shang-Chieh Chien, Anthony Yen, Kevin Huang
  • Patent number: 9570302
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a radiation-removable-material (RRM) layer over a substrate and removing a first portion of the RRM layer in a first region of the substrate by exposing the first portion of the RRM layer to a radiation beam. A second portion of the RRM layer in a second region of the substrate remains after the removing of the first portion of the RRM layer in the first region. The method also includes forming a selective-forming-layer (SFL) over the second portion of the RRM layer in the second region of the substrate and forming a material layer over the first region of the substrate.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: February 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shu-Hao Chang, Kuo-Chang Kau, Kevin Huang, Jeng-Horng Chen
  • Patent number: 9569993
    Abstract: A pixel array including first and second signal lines, an active device, a pixel electrode and selection lines is provided. The second signal lines are intersected with the first signal lines to drive the active device, and the pixel electrode is connected to the active device. The selection lines are electrically insulated to the second signal lines and intersected with the first signal lines, where at least one selective line is disposed between the adjacent two second signal lines. An amount ratio of the first signal lines and the selection lines is a1/a2, where a1?a2, and when a1 and a2 are mutually prime numbers, the selection lines are divided into a plurality of groups, and each group includes a1 selection lines electrically connected to the first signal lines, and (a2?a1) selection lines not electrically connected to the first signal lines.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: February 14, 2017
    Assignee: E Ink Holdings Inc.
    Inventors: Chi-Ming Wu, Shu-Ping Yan, Shu-Hao Chang
  • Patent number: 9542879
    Abstract: A display panel and a manufacturing method thereof are disclosed herein. The display panel includes a substrate, a peripheral circuit, a plurality of pixel electrodes, a plurality of switches, and an insulating layer. The substrate has a display region and a non-display region. At least a portion of the peripheral circuit is located on the display region of the substrate. The pixel electrodes are located on the display region of the substrate. The switches are respectively and electrically connected to the pixel electrodes, configured to be respectively switched on according to a plurality of scan signals, so as to transmit a plurality of data signals to the pixel electrodes. The insulating layer is located between the peripheral circuit and the pixel electrodes, and is configured to prevent the peripheral circuit from interfering with the pixel electrodes.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: January 10, 2017
    Assignee: E Ink Holdings Inc.
    Inventors: Kai-Mao Huang, San-Long Lin, Chi-Ming Wu, Shu-Hao Chang
  • Publication number: 20160370705
    Abstract: An EUV collector is rotated between or during operations of an EUV photolithography system. Rotating the EUV collector causes contamination to distribute more evenly over the collector's surface. This reduces the rate at which the EUV photolithography system loses image fidelity with increasing contamination and thereby increases the collector lifetime. Rotating the collector during operation of the EUV photolithography system can induce convection and reduce the contamination rate. By rotating the collector at sufficient speed, some contaminating debris can be removed through the action of centrifugal force.
    Type: Application
    Filed: August 29, 2016
    Publication date: December 22, 2016
    Inventors: Shang-Chieh Chien, Shu-Hao Chang, Jui-Ching Wu, Tsung-Yu Chen, Tzu-Hsiang Chen, Ming-Chin Chien, Chia-Chen Chen, Jeng-Horng Chen
  • Patent number: 9429858
    Abstract: An EUV collector is rotated between or during operations of an EUV photolithography system. Rotating the EUV collector causes contamination to distribute more evenly over the collector's surface. This reduces the rate at which the EUV photolithography system loses image fidelity with increasing contamination and thereby increases the collector lifetime. Rotating the collector during operation of the EUV photolithography system can induce convection and reduce the contamination rate. By rotating the collector at sufficient speed, some contaminating debris can be removed through the action of centrifugal force.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: August 30, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Chieh Chien, Shu-Hao Chang, Jui-Ching Wu, Tsung-Yu Chen, Tzu-Hsiang Chen, Ming-Chin Chien, Chia-Chen Chen, Jeng-Horng Chen
  • Publication number: 20160225610
    Abstract: The method includes performing a photolithography process which includes using a photomask to pattern a radiation beam. The photolithography process also includes exposing a target substrate to the patterned radiation beam. During the exposing of the target surface, there is a real-time monitoring for particles incident or approximate the photomask.
    Type: Application
    Filed: January 30, 2015
    Publication date: August 4, 2016
    Inventors: Shang-Chieh Chien, Shu-Hao Chang, Hsiang-Yu Chou, Kuo-Chang Kau, Shun-Der Wu, Chia-Chen Chen, Jeng-Horng Chen
  • Patent number: 9389506
    Abstract: Provided herein is a photoresist compound with improved extreme-ultraviolet lithography image performance. The photoresist includes a polymer that is free of an aromatic group and a photo acid generator (PAG) free of aromatic groups. The PAG includes an anion component and a cation component, wherein the anion component has one of the several specified chemical formulas and the cation component also has a specified chemical formula. The anion component includes a material selected from the group consisting of methyl and ethyl and the cation component includes a material selected from the group consisting of: an alkyl group, an alkenyl group, and an oxoalkyl group.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: July 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Hao Chang, Tsiao-Chen Wu, Chih-Tsung Shih
  • Publication number: 20160099260
    Abstract: A display panel includes a substrate, a plurality of first signal lines, a plurality of second signal lines, a plurality of pixel units, a plurality of transmitting lines, and a driving chip. The transmitting lines are disposed on the substrate and electrically connected to the second signal lines. The driving chip includes a plurality of first pins, a plurality of second pins, and a driving circuit. The first pins are electrically connected to the first signal lines, and the second pins are electrically connected to the transmitting lines. The first pins and the second pins are disposed alternately and evenly, such that the first signal lines and the transmitting lines do not intersect each other. The transmitting lines are disposed on the substrate evenly.
    Type: Application
    Filed: December 14, 2015
    Publication date: April 7, 2016
    Inventors: Shu-Hao CHANG, Chi-Ming WU, Ian French
  • Publication number: 20160054664
    Abstract: Systems and methods that include providing for measuring a first topographical height of a substrate at a first coordinate on the substrate and measuring a second topographical height of the substrate at a second coordinate on the substrate are provided. The measured first and second topographical heights may be provided as a wafer map. An exposure process is then performed on the substrate using the wafer map. The exposure process can include using a first focal point when exposing the first coordinate on the substrate and using a second focal plane when exposing the second coordinate on the substrate. The first focal point is determined using the first topographical height and the second focal point is determined using the second topographical height.
    Type: Application
    Filed: May 22, 2013
    Publication date: February 25, 2016
    Inventors: Jui-Ching Wu, Jeng-Horng Chen, Chia-Chen Chen, Shu-Hao Chang, Shang-Chieh Chien, Ming-Chin Chien, Anthony Yen
  • Patent number: 9268192
    Abstract: An electrophoretic display apparatus is suitable for being electrically connected to an external circuit and includes a drive array substrate, an electrophoretic display film and a first optical adhesive layer. The electrophoretic display film is disposed on the drive array substrate and includes a flexible substrate and a display medium layer. The flexible substrate has a disposed region and a bonding region. The external circuit is disposed between the flexible substrate and the drive array substrate, located in the bonding region and extends outside the drive array substrate. The display medium layer is disposed between the flexible substrate and the drive array substrate and located in the disposed region. The first optical adhesive layer is disposed between the display medium layer and the drive array substrate. A thickness of the external circuit is substantially a sum of that of the display medium layer and the first optical adhesive layer.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: February 23, 2016
    Assignee: E Ink Holdings Inc.
    Inventors: Chi-Ming Wu, Shu-Hao Chang
  • Publication number: 20160042683
    Abstract: A display panel and a manufacturing method thereof are disclosed herein. The display panel includes a substrate, a peripheral circuit, a plurality of pixel electrodes, a plurality of switches, and an insulating layer. The substrate has a display region and a non-display region. At least a portion of the peripheral circuit is located on the display region of the substrate. The pixel electrodes are located on the display region of the substrate. The switches are respectively and electrically connected to the pixel electrodes, configured to be respectively switched on according to a plurality of scan signals, so as to transmit a plurality of data signals to the pixel electrodes. The insulating layer is located between the peripheral circuit and the pixel electrodes, and is configured to prevent the peripheral circuit from interfering with the pixel electrodes.
    Type: Application
    Filed: October 13, 2015
    Publication date: February 11, 2016
    Inventors: Kai-Mao HUANG, San-Long LIN, Chi-Ming WU, Shu-Hao CHANG
  • Patent number: 9247615
    Abstract: A display panel includes a substrate, a plurality of first signal lines, a plurality of second signal lines, a plurality of pixel units, a plurality of transmitting lines, and a driving chip. The transmitting lines are disposed on the substrate and electrically connected to the second signal lines. The driving chip includes a plurality of first pins, a plurality of second pins, and a driving circuit. The first pins are electrically connected to the first signal lines, and the second pins are electrically connected to the transmitting lines. The first pins and the second pins are disposed alternately and evenly, such that the first signal lines and the transmitting lines do not intersect each other. The transmitting lines are disposed on the substrate evenly.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: January 26, 2016
    Assignee: E Ink Holdings Inc.
    Inventors: Shu-Hao Chang, Chi-Ming Wu, Ian French
  • Publication number: 20160018715
    Abstract: An electronic paper display device includes a substrate, a protection sheet, an e-ink (electronic-ink) layer, a first electrode layer, and a second electrode layer. The e-ink layer is located between the substrate and the protection sheet. The e-ink layer has a display area and a surrounding area. The display area is surrounded by the surrounding area. The first electrode layer is located between the e-ink layer and the substrate, and the first electrode layer is corresponding to the display area in position. The second electrode layer is located between the e-ink layer and the substrate, and the second electrode layer is corresponding to the surrounding area in position.
    Type: Application
    Filed: May 26, 2015
    Publication date: January 21, 2016
    Inventors: Shu-Ping YAN, Shu-Hao CHANG, Pei-Lin HUANG
  • Patent number: 9229326
    Abstract: Provided is a method of forming a pattern for an integrated circuit. The method includes forming a first layer over a substrate, wherein the first layer's etch rate is sensitive to a radiation, such as an extreme ultraviolet (EUV) radiation or an electron beam (e-beam). The method further includes forming a resist layer over the first layer and exposing the resist layer to the radiation for patterning. During the exposure, various portions of the first layer change their etch rate in response to an energy dose of the radiation received therein. The method further includes developing the resist layer, etching the first layer, and etching the substrate to form a pattern. The radiation-sensitivity of the first layer serves to reduce critical dimension variance of the pattern.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: January 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Shu-Hao Chang, Shinn-Sheng Yu, Jui-Ching Wu, Jeng-Horng Chen, Anthony Yen
  • Publication number: 20150332922
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. An inverse mask is provided. A sacrificial layer is deposited over a substrate. A patterned photoresist layer is formed over the sacrificial layer using the inverse mask. The sacrificial layer is then etched through the patterned photoresist layer to form a patterned sacrificial layer. A hard mask layer is deposited over the patterned sacrificial layer. The patterned sacrificial layer is then removed to form a second pattern on the hard mask layer.
    Type: Application
    Filed: May 16, 2014
    Publication date: November 19, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chin Chien, Jui-Ching Wu, Shu-Hao Chang, Shang-Chieh Chien, Jen-Yang Chaung, Kuo-Chang Kau, Jeng-Horng Chen
  • Patent number: 9190403
    Abstract: A display panel and a manufacturing method thereof are disclosed herein. The display panel includes a substrate, a peripheral circuit, a plurality of pixel electrodes, a plurality of switches, and an insulating layer. The substrate has a display region and a non-display region. At least a portion of the peripheral circuit is located on the display region of the substrate. The pixel electrodes are located on the display region of the substrate. The switches are respectively and electrically connected to the pixel electrodes, configured to be respectively switched on according to a plurality of scan signals, so as to transmit a plurality of data signals to the pixel electrodes. The insulating layer is located between the peripheral circuit and the pixel electrodes, and is configured to prevent the peripheral circuit from interfering with the pixel electrodes.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: November 17, 2015
    Assignee: E Ink Holdings Inc.
    Inventors: Kai-Mao Huang, San-Long Lin, Chi-Ming Wu, Shu-Hao Chang