Patents by Inventor Shu Hui Wang
Shu Hui Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961637Abstract: This disclosure relates to a stretchable composite electrode and a fabricating method thereof, and particularly relates to a stretchable composite electrode including a silver nanowire layer and a flexible polymer film and a fabricating method thereof.Type: GrantFiled: December 7, 2022Date of Patent: April 16, 2024Assignee: TPK ADVANCED SOLUTIONS INC.Inventors: Wei Sheng Chen, Ching Mao Huang, Jia Hui Zhou, Huan Ran Yu, Shu Xiong Wang, Chin Hui Lee
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Publication number: 20240047273Abstract: Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes receiving a workpiece including a first semiconductor fin and a second semiconductor fin penetrating from a substrate and separated by a first isolation feature, and a gate structure intersecting the first semiconductor fin and the second semiconductor fin. The method also includes removing the gate structure and portions of the first semiconductor fin, the second semiconductor fin, and the first isolation feature disposed directly under the gate structure to form a fin isolation trench, forming a dielectric layer over the workpiece to substantially fill the fin isolation trench, and planarizing the dielectric layer to form a fin isolation structure in the fin isolation trench.Type: ApplicationFiled: August 4, 2022Publication date: February 8, 2024Inventors: Hsin-Che Chiang, Jyun-Hong Huang, Chi-Wei Wu, Shu-Hui Wang, Jeng-Ya Yeh
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Publication number: 20230361120Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.Type: ApplicationFiled: July 20, 2023Publication date: November 9, 2023Inventors: Shun-Jang LIAO, Chia-Chun LIAO, Shu-Hui WANG, Shih-Hsun CHANG
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Patent number: 11764218Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.Type: GrantFiled: June 21, 2021Date of Patent: September 19, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shun-Jang Liao, Chia-Chun Liao, Shu-Hui Wang, Shih-Hsun Chang
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Publication number: 20230268406Abstract: A method includes forming a semiconductor fin over a substrate; forming a gate structure over the semiconductor fin, the gate structure comprising: a first metallic layer; a second metallic layer over the first metallic layer, wherein the first metallic layer is a metal compound of a first element and a second element and the second metallic layer is a single-element metal of the second element; and an oxide layer between the first metallic layer and the second metallic layer.Type: ApplicationFiled: April 24, 2023Publication date: August 24, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Che CHIANG, Ju-Yuan TZENG, Chun-Sheng LIANG, Chih-Yang YEH, Shu-Hui WANG, Jeng-Ya David YEH
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Patent number: 11670697Abstract: A semiconductor device includes a substrate comprising a semiconductor fin, a gate structure over the semiconductor fin, and source/drain structures over the semiconductor fin and on opposite sides of the gate structure. The gate stack comprises a high-k dielectric layer; a first work function metal layer over the high-k dielectric layer; an oxide of the first work function metal layer over the first work function metal layer; and a second work function metal layer over the oxide of the first work function metal layer, in which the first and second work function metal layers have different compositions; and a gate electrode over the second work function metal layer.Type: GrantFiled: June 21, 2021Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Che Chiang, Ju-Yuan Tzeng, Chun-Sheng Liang, Chih-Yang Yeh, Shu-Hui Wang, Jeng-Ya David Yeh
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Patent number: 11404418Abstract: A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.Type: GrantFiled: September 28, 2020Date of Patent: August 2, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Chun Liao, Chun-Sheng Liang, Shu-Hui Wang, Shih-Hsun Chang, Yi-Jen Chen
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Patent number: 11295990Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.Type: GrantFiled: January 6, 2020Date of Patent: April 5, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang
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Patent number: 11145730Abstract: A semiconductor device includes a substrate, a first gate structure, a plurality of first gate spacers, a second gate structure, and a plurality of second gate spacers. The substrate has a first fin structure and a second fin structure. The first gate structure is over the first fin structure, in which the first gate structure includes a first high dielectric constant material and a first metal. A bottom surface of the first high dielectric constant material is higher than bottom surfaces of the first gate spacers. The second gate structure is narrower than the first gate structure and over the second fin structure, in which the second gate structure includes a second high dielectric constant material and a second metal. A bottom surface of the second high dielectric constant material is lower than bottom surfaces of the second gate spacers.Type: GrantFiled: November 8, 2019Date of Patent: October 12, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Che Chiang, Ju-Yuan Tzeng, Chun-Sheng Liang, Shu-Hui Wang, Chih-Yang Yeh, Jeng-Ya David Yeh
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Publication number: 20210313328Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.Type: ApplicationFiled: June 21, 2021Publication date: October 7, 2021Inventors: Shun-Jang LIAO, Chia-Chun LIAO, Shu-Hui WANG, Shih-Hsun CHANG
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Publication number: 20210313437Abstract: A semiconductor device includes a substrate comprising a semiconductor fin, a gate structure over the semiconductor fin, and source/drain structures over the semiconductor fin and on opposite sides of the gate structure. The gate stack comprises a high-k dielectric layer; a first work function metal layer over the high-k dielectric layer; an oxide of the first work function metal layer over the first work function metal layer; and a second work function metal layer over the oxide of the first work function metal layer, in which the first and second work function metal layers have different compositions; and a gate electrode over the second work function metal layer.Type: ApplicationFiled: June 21, 2021Publication date: October 7, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Che CHIANG, Ju-Yuan TZENG, Chun-Sheng LIANG, Chih-Yang YEH, Shu-Hui WANG, Jeng-Ya David YEH
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Patent number: 11043567Abstract: A semiconductor device includes a substrate, a gate stack. The substrate includes a semiconductor fin. The gate stack is disposed on the semiconductor fin. The gate stack includes a dielectric layer disposed over the semiconductor fin, and a metal stack disposed over the dielectric layer and having a first metallic layer and a second metallic layer over the first metallic layer, and a gate electrode disposed over the metal stack. The first metallic layer and the second metallic layer have a first element, and a percentage of the first element in the first metallic layer is greater than that in the second metallic layer.Type: GrantFiled: August 28, 2018Date of Patent: June 22, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Che Chiang, Ju-Yuan Tzeng, Chun-Sheng Liang, Chih-Yang Yeh, Shu-Hui Wang, Jeng-Ya David Yeh
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Patent number: 11043385Abstract: A semiconductor device includes a semiconductor fin, a gate structure, a source epitaxy structure and a drain epitaxy structure. The semiconductor fin extends along a first direction above a substrate. The gate structure extends across the semiconductor fin along a second direction different from the first direction. The gate structure includes a gate dielectric layer wrapping around the semiconductor fin and a chlorine-containing N-work function metal layer wrapping around the gate dielectric layer. The source epitaxy structure and the drain epitaxy structure are on opposite sides of the gate structure, respectively.Type: GrantFiled: September 4, 2020Date of Patent: June 22, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Li-Jung Liu, Chun-Sheng Liang, Shu-Hui Wang
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Patent number: 11043491Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.Type: GrantFiled: December 20, 2019Date of Patent: June 22, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shun-Jang Liao, Chia-Chun Liao, Shu-Hui Wang, Shih-Hsun Chang
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Publication number: 20210013205Abstract: A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.Type: ApplicationFiled: September 28, 2020Publication date: January 14, 2021Inventors: Chia-Chun LIAO, Chun-Sheng LIANG, Shu-Hui WANG, Shih-Hsun CHANG, Yi-Jen CHEN
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Publication number: 20200402803Abstract: A semiconductor device includes a semiconductor fin, a gate structure, a source epitaxy structure and a drain epitaxy structure. The semiconductor fin extends along a first direction above a substrate. The gate structure extends across the semiconductor fin along a second direction different from the first direction. The gate structure includes a gate dielectric layer wrapping around the semiconductor fin and a chlorine-containing N-work function metal layer wrapping around the gate dielectric layer. The source epitaxy structure and the drain epitaxy structure are on opposite sides of the gate structure, respectively.Type: ApplicationFiled: September 4, 2020Publication date: December 24, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Li-Jung LIU, Chun-Sheng LIANG, Shu-Hui WANG
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Patent number: 10872963Abstract: A semiconductor structure can include a resistor on a substrate formed simultaneously with other devices, such as transistors. A diffusion barrier layer formed on a substrate is patterned to form a resistor and barrier layers under a transistor gate. A filler material, a first connector, and a second connector are formed on the resistor at the same manner and time as the gate of the transistor. The filler material is removed to form a resistor on a substrate.Type: GrantFiled: May 20, 2019Date of Patent: December 22, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hua Feng Chen, Shu-Hui Wang, Mu-Chi Chiang
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Patent number: 10867806Abstract: A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer.Type: GrantFiled: August 30, 2019Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Che Chiang, Ju-Yuan Tzeng, Chun-Sheng Liang, Shu-Hui Wang, Kuo-Hua Pan
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Patent number: 10825813Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.Type: GrantFiled: July 30, 2018Date of Patent: November 3, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shun-Jang Liao, Chia-Chun Liao, Shu-Hui Wang, Shih-Hsun Chang
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Patent number: 10790283Abstract: A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.Type: GrantFiled: April 29, 2019Date of Patent: September 29, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Chun Liao, Chun-Sheng Liang, Shu-Hui Wang, Shih-Hsun Chang, Yi-Jen Chen