Patents by Inventor Shu Hui Wang

Shu Hui Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210013205
    Abstract: A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Inventors: Chia-Chun LIAO, Chun-Sheng LIANG, Shu-Hui WANG, Shih-Hsun CHANG, Yi-Jen CHEN
  • Publication number: 20200402803
    Abstract: A semiconductor device includes a semiconductor fin, a gate structure, a source epitaxy structure and a drain epitaxy structure. The semiconductor fin extends along a first direction above a substrate. The gate structure extends across the semiconductor fin along a second direction different from the first direction. The gate structure includes a gate dielectric layer wrapping around the semiconductor fin and a chlorine-containing N-work function metal layer wrapping around the gate dielectric layer. The source epitaxy structure and the drain epitaxy structure are on opposite sides of the gate structure, respectively.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Jung LIU, Chun-Sheng LIANG, Shu-Hui WANG
  • Patent number: 10872963
    Abstract: A semiconductor structure can include a resistor on a substrate formed simultaneously with other devices, such as transistors. A diffusion barrier layer formed on a substrate is patterned to form a resistor and barrier layers under a transistor gate. A filler material, a first connector, and a second connector are formed on the resistor at the same manner and time as the gate of the transistor. The filler material is removed to form a resistor on a substrate.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: December 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hua Feng Chen, Shu-Hui Wang, Mu-Chi Chiang
  • Patent number: 10867806
    Abstract: A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Che Chiang, Ju-Yuan Tzeng, Chun-Sheng Liang, Shu-Hui Wang, Kuo-Hua Pan
  • Publication number: 20200345988
    Abstract: A pipeline collector is used for bundling at least one hose. The pipeline collector comprises at least one bundling member corresponding to the hoses and is characterized in that each of the bundling members comprises a bundling body, a first top edge positioned at one side of the bundling body, a second top edge defined at the other side of the bundling body relative to the first top edge, and a first accommodation area which is recessed from the surface of the bundling body relative to the hoses and penetrates through the first top edge and the second top edge, wherein a profile of the first accommodation area is non-orthogonally disposed relative to the first top edge or the second top edge.
    Type: Application
    Filed: May 1, 2019
    Publication date: November 5, 2020
    Inventors: CHING-LUNG KUO, JHI-JOUNG WANG, YU-CHEN TUNG, PEI-CHEN HUANG, CHIA-CHEN HSU, SHU-HUI HU, JUI-YU WENG
  • Patent number: 10825813
    Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: November 3, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shun-Jang Liao, Chia-Chun Liao, Shu-Hui Wang, Shih-Hsun Chang
  • Patent number: 10790283
    Abstract: A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: September 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Chun Liao, Chun-Sheng Liang, Shu-Hui Wang, Shih-Hsun Chang, Yi-Jen Chen
  • Patent number: 10770299
    Abstract: A semiconductor device includes a semiconductor fin and a gate structure. The semiconductor fin extends along a first direction above a substrate. The gate structure extends across the semiconductor fin along a second direction substantially perpendicular to the first direction. The gate structure includes a chlorine-containing N-work function metal layer wrapping around the semiconductor fin, and a filling metal over and in contact with the chlorine-containing N-work function metal layer.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Jung Liu, Chun-Sheng Liang, Shu-Hui Wang
  • Publication number: 20200152521
    Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 14, 2020
    Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang
  • Publication number: 20200135477
    Abstract: A semiconductor device includes a semiconductor fin and a gate structure. The semiconductor fin extends along a first direction above a substrate. The gate structure extends across the semiconductor fin along a second direction substantially perpendicular to the first direction. The gate structure includes a chlorine-containing N-work function metal layer wrapping around the semiconductor fin, and a filling metal over and in contact with the chlorine-containing N-work function metal layer.
    Type: Application
    Filed: December 23, 2019
    Publication date: April 30, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Jung LIU, Chun-Sheng LIANG, Shu-Hui WANG
  • Publication number: 20200135734
    Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 30, 2020
    Inventors: Shun-Jang LIAO, Chia-Chun LIAO, Shu-Hui WANG, Shih-Hsun CHANG
  • Patent number: 10637374
    Abstract: A magnetic sensor integrated circuit, a motor component and an application apparatus are provided. The integrated circuit includes: an input port, an output port, a magnetic field detection circuit and an output control circuit. The magnetic field detection circuit detects an external magnetic field and outputs magnetic field detection information. The output control circuit enables, at least based on the magnetic field detection information, the integrated circuit to switch at least between a first state, in which a current flows from the output port to an outside of the integrated circuit, and a second state, in which a current flows from the outside of the integrated circuit to the output port.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: April 28, 2020
    Assignee: JOHNSON ELECTRIC INTERNATIONAL AG
    Inventors: Chi Ping Sun, Fei Xin, Ken Wong, Shing Hin Yeung, Shu Juan Huang, Yun Long Jiang, Yue Li, Bao Ting Liu, En Hui Wang, Xiu Wen Yang, Li Sheng Liu, Yan Yun Cui
  • Publication number: 20200075741
    Abstract: A semiconductor device includes a substrate, a first gate structure, a plurality of first gate spacers, a second gate structure, and a plurality of second gate spacers. The substrate has a first fin structure and a second fin structure. The first gate structure is over the first fin structure, in which the first gate structure includes a first high dielectric constant material and a first metal. A bottom surface of the first high dielectric constant material is higher than bottom surfaces of the first gate spacers. The second gate structure is narrower than the first gate structure and over the second fin structure, in which the second gate structure includes a second high dielectric constant material and a second metal. A bottom surface of the second high dielectric constant material is lower than bottom surfaces of the second gate spacers.
    Type: Application
    Filed: November 8, 2019
    Publication date: March 5, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Che CHIANG, Ju-Yuan TZENG, Chun-Sheng LIANG, Shu-Hui WANG, Chih-Yang YEH, Jeng-Ya David YEH
  • Patent number: 10535653
    Abstract: A semiconductor structure includes a pair of gate structures and an isolation structure. Each of the gate structures includes a work function metal, a gate, and a barrier layer between the work function metal and the gate. The isolation structure is disposed between the gate structures. The barrier layer covers a sidewall of the isolation structure.
    Type: Grant
    Filed: December 17, 2017
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jen Chen, Chun-Sheng Liang, Shu-Hui Wang, Shih-Hsun Chang, Hsin-Che Chiang
  • Patent number: 10529629
    Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: January 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang
  • Publication number: 20190393326
    Abstract: A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer.
    Type: Application
    Filed: August 30, 2019
    Publication date: December 26, 2019
    Inventors: Hsin-Che CHIANG, Ju-Yuan TZENG, Chun-Sheng LIANG, Shu-Hui WANG, Kuo-Hua PAN
  • Patent number: 10515811
    Abstract: A semiconductor device includes a semiconductor substrate, a filling conductor, an N-work function conductor layer and a gate dielectric layer. The filling conductor is over the semiconductor substrate. The N-work function conductor layer wraps around the filling conductor. The N-work function conductor layer comprises chlorine. The gate dielectric layer is between the N-work function conductor layer and the semiconductor.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Jung Liu, Chun-Sheng Liang, Shu-Hui Wang
  • Patent number: 10515964
    Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shun-Jang Liao, Chia-Chun Liao, Shu-Hui Wang, Shih-Hsun Chang
  • Patent number: 10475895
    Abstract: A semiconductor device includes a substrate, a first dielectric layer, a first device and a second device. The first dielectric layer is disposed on the substrate. The first device is disposed on the first dielectric layer on a first region of the substrate, and includes two first spacers, a second dielectric layer and a first gate structure. The first spacers are separated to form a first trench. The second dielectric layer is disposed on side surfaces and a bottom surface of the first trench. The first gate structure is disposed on the second dielectric layer. The second device is disposed on a second region of the substrate, and includes two second spacers and a second gate structure. The second spacers are disposed on the first dielectric layer and are separated to form a second trench. The second gate structure is disposed on the substrate within the second trench.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Che Chiang, Ju-Yuan Tzeng, Chun-Sheng Liang, Shu-Hui Wang, Chih-Yang Yeh, Jeng-ya David Yeh
  • Publication number: 20190333826
    Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.
    Type: Application
    Filed: April 30, 2018
    Publication date: October 31, 2019
    Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang