Patents by Inventor Shu Hui Wang
Shu Hui Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10262878Abstract: A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor. The substantially fluorine-free metal layer includes an amount of fluorine less than about 5 atomic percent.Type: GrantFiled: October 9, 2018Date of Patent: April 16, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Jung Liu, Chih-Pin Tsao, Chia-Wei Soong, Jyh-Huei Chen, Shu-Hui Wang, Shih-Hsun Chang
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Publication number: 20190088763Abstract: A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer.Type: ApplicationFiled: November 16, 2018Publication date: March 21, 2019Inventors: Hsin-Che CHIANG, Ju-Yuan TSENG, Chun-Sheng LIANG, Shu-Hui WANG, Kuo-Hua PAN
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Publication number: 20190051542Abstract: A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor. The substantially fluorine-free metal layer includes an amount of fluorine less than about 5 atomic percent.Type: ApplicationFiled: October 9, 2018Publication date: February 14, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Jung LIU, Chih-Pin Tsao, Chia-Wei Soong, Jyh-Huei Chen, Shu-Hui Wang, Shih-Hsun Chang
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Patent number: 10164065Abstract: In a method for manufacturing a semiconductor device, a first raised structure is formed on a surface of a substrate. The first raised structure includes a top surface and a side surface adjoining the top surface. The side surface includes an upper portion, a middle portion, and a lower portion. A deposition operation is performed with a precursor to form a first film on the top surface, the upper portion and the lower portion of the side surface, and the surface of the substrate. Performing the deposition operation includes controlling a saturated vapor pressure of the precursor. A re-deposition operation is performed on the first film and the first raised structure, so as to form a film structure. A thickness of the film structure on the middle portion of the side surface is smaller than a thickness of the film structure on the top surface.Type: GrantFiled: June 22, 2017Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Che Chiang, Ju-Yuan Tzeng, Chun-Sheng Liang, Shu-Hui Wang, Chih-Yang Yeh, Jeng-Ya David Yeh
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Publication number: 20180350956Abstract: In a method for manufacturing a semiconductor device, a first raised structure is formed on a surface of a substrate. The first raised structure includes a top surface and a side surface adjoining the top surface. The side surface includes an upper portion, a middle portion, and a lower portion. A deposition operation is performed with a precursor to form a first film on the top surface, the upper portion and the lower portion of the side surface, and the surface of the substrate. Performing the deposition operation includes controlling a saturated vapor pressure of the precursor. A re-deposition operation is performed on the first film and the first raised structure, so as to form a film structure. A thickness of the film structure on the middle portion of the side surface is smaller than a thickness of the film structure on the top surface.Type: ApplicationFiled: June 22, 2017Publication date: December 6, 2018Inventors: Hsin-Che CHIANG, Ju-Yuan TZENG, Chun-Sheng LIANG, Shu-Hui WANG, Chih-Yang YEH, Jeng-Ya David YEH
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Publication number: 20180342595Abstract: A semiconductor device includes a substrate, a first dielectric layer, a first device and a second device. The first dielectric layer is disposed on the substrate. The first device is disposed on the first dielectric layer on a first region of the substrate, and includes two first spacers, a second dielectric layer and a first gate structure. The first spacers are separated to form a first trench. The second dielectric layer is disposed on side surfaces and a bottom surface of the first trench. The first gate structure is disposed on the second dielectric layer. The second device is disposed on a second region of the substrate, and includes two second spacers and a second gate structure. The second spacers are disposed on the first dielectric layer and are separated to form a second trench. The second gate structure is disposed on the substrate within the second trench.Type: ApplicationFiled: June 21, 2017Publication date: November 29, 2018Inventors: Hsin-Che CHIANG, Ju-Yuan TZENG, Chun-Sheng LIANG, Shu-Hui WANG, Chih-Yang YEH, Jeng-Ya David YEH
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Publication number: 20180337181Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.Type: ApplicationFiled: July 30, 2018Publication date: November 22, 2018Inventors: Shun-Jang LIAO, Chia-Chun LIAO, Shu-Hui WANG, Shih-Hsun CHANG
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Patent number: 10134873Abstract: A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer.Type: GrantFiled: November 18, 2016Date of Patent: November 20, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Che Chiang, Ju-Yuan Tzeng, Chun-Sheng Liang, Shu-Hui Wang, Kuo-Hua Pan
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Publication number: 20180323303Abstract: A semiconductor device includes a semiconductor substrate, a filling conductor, an N-work function conductor layer and a gate dielectric layer. The filling conductor is over the semiconductor substrate. The N-work function conductor layer wraps around the filling conductor. The N-work function conductor layer comprises chlorine. The gate dielectric layer is between the N-work function conductor layer and the semiconductor.Type: ApplicationFiled: June 29, 2018Publication date: November 8, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Li-Jung LIU, Chun-Sheng LIANG, Shu-Hui WANG
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Patent number: 10109507Abstract: A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor. The substantially fluorine-free metal layer includes an amount of fluorine less than about 5 atomic percent.Type: GrantFiled: May 31, 2017Date of Patent: October 23, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Jung Liu, Chih-Pin Tsao, Chia-Wei Soong, Jyh-Huei Chen, Shu-Hui Wang, Shih-Hsun Chang
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Patent number: 10043910Abstract: A semiconductor device includes a semiconductor substrate, a plurality of gate spacers and a gate stack. The gate spacers are over the semiconductor substrate. The gate stack is over the semiconductor substrate and between the gate spacers. The gate stack includes a carbon-containing titanium nitride layer and an N-work function conductor layer over the carbon-containing titanium nitride layer.Type: GrantFiled: April 26, 2017Date of Patent: August 7, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Li-Jung Liu, Chun-Sheng Liang, Shu-Hui Wang
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Patent number: 10037995Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.Type: GrantFiled: November 18, 2016Date of Patent: July 31, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shun-Jang Liao, Chia-Chun Liao, Shu-Hui Wang, Shih-Hsun Chang
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Publication number: 20180145149Abstract: A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer.Type: ApplicationFiled: November 18, 2016Publication date: May 24, 2018Inventors: Hsin-Che CHIANG, Ju-Yuan TZENG, Chun-Sheng LIANG, Shu-Hui WANG, Kuo-Hua PAN
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Publication number: 20180108653Abstract: A semiconductor structure includes a pair of gate structures and an isolation structure. Each of the gate structures includes a work function metal, a gate, and a barrier layer between the work function metal and the gate. The isolation structure is disposed between the gate structures. The barrier layer covers a sidewall of the isolation structure.Type: ApplicationFiled: December 17, 2017Publication date: April 19, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Jen CHEN, Chun-Sheng LIANG, Shu-Hui WANG, Shih-Hsun CHANG, Hsin-Che CHIANG
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Patent number: 9947594Abstract: A semiconductor device includes a first semiconductor channel, a second semiconductor channel, a first gate stack and a second gate stack. The first gate stack includes N-work function metal present on the first semiconductor channel. The second gate stack includes N-work function metal present on the second semiconductor channel. The N-work function metal in the first gate stack and the second gate stack are substantially different. The difference includes at least one of N-work function metal type and N-work function metal amount.Type: GrantFiled: September 19, 2016Date of Patent: April 17, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Yang Yeh, Shun-Jang Liao, Shu-Hui Wang, Chun-Sheng Liang, Kuo-Hua Pan, Jeng-Ya David Yeh
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Publication number: 20180082908Abstract: A semiconductor device includes a first semiconductor channel, a second semiconductor channel, a first gate stack and a second gate stack. The first gate stack includes N-work function metal present on the first semiconductor channel. The second gate stack includes N-work function metal present on the second semiconductor channel. The N-work function metal in the first gate stack and the second gate stack are substantially different. The difference includes at least one of N-work function metal type and N-work function metal amount.Type: ApplicationFiled: September 19, 2016Publication date: March 22, 2018Inventors: Chih-Yang Yeh, Shun-Jang Liao, Shu-Hui Wang, Chun-Sheng Liang, Kuo-Hua Pan, Jeng-Ya David Yeh
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Publication number: 20180019242Abstract: A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.Type: ApplicationFiled: July 15, 2016Publication date: January 18, 2018Inventors: Chia-Chun LIAO, Chun-Sheng LIANG, Shu-Hui WANG, Shih-Hsun CHANG, Yi-Jen CHEN
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Patent number: 9859273Abstract: A process of manufacturing a semiconductor structure is provided. The process begins with forming a work function metal layer on a substrate, and a hardmask is covered over the work function metal layer. A trench is formed to penetrate the hardmask and the work function metal layer, and an isolation structure is filled in the trench.Type: GrantFiled: May 28, 2015Date of Patent: January 2, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Jen Chen, Chun-Sheng Liang, Shu-Hui Wang, Shih-Hsun Chang, Hsin-Che Chiang
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Publication number: 20170352559Abstract: A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor. The substantially fluorine-free metal layer includes an amount of fluorine less than about 5 atomic percent.Type: ApplicationFiled: May 31, 2017Publication date: December 7, 2017Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Jung LIU, Chih-Pin TSAO, Chia-Wei SOONG, Jyh-Huei CHEN, Shu-Hui WANG, Shih-Hsun CHANG
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Patent number: 9799566Abstract: A semiconductor device includes a first semiconductor channel, a second semiconductor channel, a first gate stack and a second gate stack. The first gate stack is present on the first semiconductor channel. The first gate stack includes a first work function layer and a first interposing layer present between the first semiconductor channel and the first work function layer. The second gate stack is present on the second semiconductor channel. The second gate stack includes a second work function layer and a second interposing layer present between the second semiconductor channel and the second work function layer. The first interposing layer and the second interposing layer are different at least in tantalum nitride amount.Type: GrantFiled: September 22, 2016Date of Patent: October 24, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shun-Jang Liao, Shu-Hui Wang, Shih-Hsun Chang