Abstract: Embodiments of the disclosure, there is provided a method, a system for adjusting the memory, and a semiconductor device. The method for adjusting the memory includes: acquiring a mapping relationship between a temperature of a transistor, an equivalent width-length ratio of a sense amplifier transistor in a sense amplifier and an actual time at which the data is written into the memory; acquiring a current temperature of the transistor; and adjusting the equivalent width-length ratio, based on the current temperature and the mapping relationship, so that the actual time at which the data is written into the memory corresponding to the adjusted equivalent width-length ratio is within a preset writing time.

Abstract: A base die is configured to receive first data and first encoded data in a writing phase, perform first error checking and correction processing, wherein the first encoded data is obtained by performing a first error correction code encoding processing on the first data, and transmit second data to a memory die in the writing phase, wherein the second data includes a first data after the first error checking and correction processing; the base die is further configured to receive the second data from the memory die in a reading phase, perform second error correction code encoding processing on the second data to generate second encoded data, and transmit third data in the reading phase, wherein the third data includes the second encoded data and the first data after the first error checking and correction processing.

Abstract: A base die is configured to: receive first data in a writing phase, perform error correction code encoding processing to generate encoded data, and transmit second data to a memory die in the writing phase, wherein the second data includes the first data and the encoded data; and receive the second data from the memory die in a reading phase, perform error checking and correction processing, and transmit third data in the reading phase, wherein the third data is the first data after the error checking and correction processing.

Abstract: Embodiments of this application provide a method and system for adjusting a memory, and a semiconductor device. The method for adjusting a memory includes: acquiring a mapping relationship among a temperature of a transistor, a substrate bias voltage of a sense amplification transistor in a sense amplifier, and an actual data writing time of the memory; acquiring a current temperature of the transistor; and adjusting the substrate bias voltage on the basis of the current temperature and the mapping relationship, such that an actual data writing time corresponding to an adjusted substrate bias voltage is within a preset writing time.

Abstract: A memory chip is applied to the memory system, and the memory chip is configured to perform counting and obtain a count value after the memory chip is powered on and started, wherein the count value is used to represent a process corner of the memory chip, the memory chip further has a reference voltage with an adjustable value, the value of the reference voltage is adjustable based on the count value, and the memory chip adjusts, based on the reference voltage, a delay from reading out data from a memory cell to outputting the data through a data port.

Abstract: A memory is provided. The memory includes: a control chip; and a plurality of storage chips, in which the plurality of storage chips are electrically connected with the control chip via a common communication channel, the plurality of storage chips are configured to perform information interaction with the control chip by adopting different clock edges of a first clock signal, the first clock signal has a first clock cycle, the different clock edges include two consecutive rising edges and/or two consecutive falling edges, the plurality of storage chips are further configured to receive a second clock signal and distinguish the different clock edges based on the second clock signal, and a second clock cycle of the second clock signal is greater than the first clock cycle.

Abstract: A memory system includes: a plurality of memory chips, wherein each of the memory chips has a parameter used to characterize a process corner of the memory chip; and a controller, wherein the controller is configured to: obtain the parameter of each of the memory chips, and adjust, based on the parameter, a delay of a read command sent to the memory chip corresponding to the parameter.

Abstract: A memory includes: a control chip; and a plurality of storage chips, in which the plurality of storage chips are electrically connected with the control chip via a common communication channel, the plurality of storage chips include a first storage chip set and a second storage chip set, the storage chips in the first storage chip set are configured to perform information interaction with the control chip by adopting a first clock signal, the storage chips in the second storage chip set are configured to perform information interaction with the control chip by adopting a second clock signal, and phase of the first clock signal is different from phase of the second clock signal.

Abstract: A method for adjusting the memory includes: acquiring a mapping relationship between a temperature of a transistor, a gate voltage of the transistor, and an actual time at which data is written into the memory; acquiring a current temperature of the transistor; and adjusting the gate voltage, based on the current temperature and the mapping relationship, so that the actual time at which the data is written into the memory corresponding to the adjusted gate voltage is within a preset writing time.

Abstract: A reading and writing method for a memory device and a memory device are provided. The memory device includes a memory chip. The reading and writing method of the memory device includes that: during operation of the memory chip, the temperature of the memory chip is measured, and a writing recovery time of the memory chip is adjusted according to the temperature.

Abstract: A memory chip stores a characterization parameter for characterizing a process corner of the memory chip, the memory chip further has a reference voltage with an adjustable value, the value of the reference voltage is adjustable based on the characterization parameter, and the memory chip adjusts, based on the reference voltage, a delay from reading out data from a memory cell to outputting the data through a data port.

Abstract: Memory includes at least one memory chip, a command port and a data port. Each memory chip includes at least one channel. Each channel includes multiple banks that are configured to perform read and write operations alternately. The command port is configured to receive command signals at a preset edge of a command clock, and the command signals are configured to control the read and write operations of the banks. The data port is configured to receive data signals to be written into the banks or transmit data signals at preset edges of a data clock. The command port includes a row address port and a column address port. The row address port is configured to receive a row address signal at a position of a target memory cell, and the column address port is configured to receive a column address signal at a position of the target memory cell.

Abstract: A memory device includes: a plurality of channels, each including a memory cell array, the memory cell array including a normal cell array, the normal cell array including normal memory cells, and each of the normal memory cells being a volatile memory cell; a testing control circuit, configured to control testing of the normal cell array in the plurality of channels in response to a testing instruction, and to determine an access address of a normal memory cell failing the testing in the normal cell array in the plurality of channels to be a failure address; and a non-volatile memory cell array which includes a plurality of non-volatile memory cells and is configured to receive and store the failure address from the testing control circuit.

Abstract: A base die is configured to: receive a first data and a first encoded data in a writing phase, where the first encoded data is obtained by performing a first error correction code (ECC) encoding processing on the first data, perform a second ECC encoding processing on a first sub-data to generate a second encoded data, and transmit a second data to a memory die in the writing phase; where the second data includes the first sub-data, a second sub-data, the first encoded data, and the second encoded data; the base die is further configured to: receive the second data from the memory die in a reading phase, perform first error checking and correction processing on the first sub-data and the second encoded data, and transmit a third data in the reading phase.

Abstract: A base die is configured to receive a first data and a first encoded data in a writing phase, where the first encoded data is obtained by performing a first error correction code (ECC) encoding processing on the first data, perform a second ECC encoding processing on the first data to generate a second encoded data, and transmit a second data to a memory die in the writing phase, where the second data includes the first data, the first encoded data, and the second encoded data. The base die is further configured to receive the second data from the memory die in a reading phase, perform a first error checking and correction processing on the first data and the second encoded data, and transmit a third data in the reading phase.

Abstract: A method for regulating the memory includes operations as follows. A mapping relationship among temperatures of a transistor, body bias voltages of the transistor, and data writing time of the memory is acquired, a current temperature of the transistor is acquired, the body bias voltage is regulated based on the current temperature and the mapping relationship, to enable the data writing time corresponding to the regulated body bias voltage to be within a preset writing time.

Abstract: The present disclosure provides a memory device, wherein: an address latch can output a block selection control signal according to a block selection enable signal; a test mode selection unit can output a test mode selection signal according to a test mode selection instruction signal; a block selection unit outputs a block selection signal according to a mode selection signal and a block selection enable signal; when the memory enters a first test mode according to the test mode selection signal, an output buffer disables some of the input/output ports, and sequentially outputs the first input/output data and the second input/output data through un-disabled the input/output ports. The memory device according to the present disclosure can occupy less input/output ports of a test machine.

Abstract: Embodiments of the disclosure, there is provided a method, a system for adjusting the memory, and a semiconductor device. The method for adjusting the memory includes: acquiring a mapping relationship between a temperature of a transistor, an equivalent width-length ratio of a sense amplifier transistor in a sense amplifier and an actual time at which the data is written into the memory; acquiring a current temperature of the transistor; and adjusting the equivalent width-length ratio, based on the current temperature and the mapping relationship, so that the actual time at which the data is written into the memory corresponding to the adjusted equivalent width-length ratio is within a preset writing time.

Abstract: A chip package structure and a storage system are provided. The chip package structure includes a chipset, a first Re-Distribution Layer (RDL), and a bonding pad region. The chipset includes a plurality of chips distributed horizontally. The first RDL is disposed on a first surface of the chipset. The bonding pad region includes a plurality of bonding pads, the plurality of bonding pads are located on a side surface of the first RDL away from the chipset, and the plurality of bonding pads are connected to the plurality of chips through the first RDL.

Abstract: A memory system includes: a plurality of memory chips, wherein each of the memory chips has a parameter used to characterize a process corner of the memory chip; and a controller, wherein the controller is configured to: obtain the parameter of each of the memory chips, and adjust, based on the parameter, a delay of a read command sent to the memory chip corresponding to the parameter.