Patents by Inventor Shu-Ru Wang
Shu-Ru Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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TWO-PORT TERNARY CONTENT ADDRESSABLE MEMORY AND LAYOUT PATTERN THEREOF, AND ASSOCIATED MEMORY DEVICE
Publication number: 20200365207Abstract: A two-port ternary content addressable memory (TCAM) and layout pattern thereof, and associated memory device are provided. The two-port TCAM may include a first storage unit, a second storage unit, a set of first search terminals, a set of second search terminals, a first comparison circuit, a second comparison circuit, a first match terminal and a second match terminal, wherein the first comparison circuit is respectively coupled to the first storage unit, the second storage unit, the set of first search terminals and the first match terminal, and the second comparison circuit is respectively coupled to the first storage unit, the second storage unit, the set of second search terminals and the second match terminal. First search data and second search data may be concurrently inputted into the two-port TCAM for determining whether the first search data and the second search data match content data within the two-port TCAM.Type: ApplicationFiled: June 12, 2019Publication date: November 19, 2020Inventors: Chun-Hsien Huang, Ching-Cheng Lung, Yu-Tse Kuo, Shu-Ru Wang, Chun-Yen Tseng -
Patent number: 10706914Abstract: A static random access memory (SRAM) structure includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, a second inverter comprising a second pull-up transistor and a second pull-down transistor, a first pass transistor coupled to the first inverter, and a second pass transistor coupled to the second inverter. Preferably, the first inverter is coupled to a first tunnel magnetoresistance (TMR) structure and the second inverter is coupled to a second TMR structure.Type: GrantFiled: June 26, 2018Date of Patent: July 7, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Yen Tseng, Ching-Cheng Lung, Yu-Tse Kuo, Chun-Hsien Huang, Hsin-Chih Yu, Shu-Ru Wang
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Publication number: 20200083232Abstract: A layout pattern of a static random access memory (SRAM) preferably includes a first inverter and a second inverter. Preferably, the first inverter includes a first gate structure extending along a first direction on a substrate, in which the first gate structure includes a gate of a first pull-up device (PL1) and a gate of a first pull-down device (PD1). The second inverter includes a second gate structure extending along the first direction on the substrate, in which the second gate structure includes a gate of a second pull-up device (PL2) and a gate of a second pull-down device (PD2) and the gate of the PD1 is directly under the gate of the PD2.Type: ApplicationFiled: October 5, 2018Publication date: March 12, 2020Inventors: Chun-Hsien Huang, Ching-Cheng Lung, Yu-Tse Kuo, Shu-Ru Wang, Chun-Yen Tseng
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Patent number: 10559573Abstract: A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise a first fin structure, the PG2A and the PG2B comprise a second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2, the first local interconnection layer and the second local interconnection layer are monolithically formed structures respectively.Type: GrantFiled: October 16, 2018Date of Patent: February 11, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shu-Ru Wang, Ching-Cheng Lung, Yu-Tse Kuo, Chien-Hung Chen, Chun-Hsien Huang, Li-Ping Huang, Chun-Yen Tseng, Meng-Ping Chuang
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Patent number: 10522551Abstract: A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure has a first line terminal. The second circuit structure has a second line terminal. The first line terminal and the second line terminal are formed in a first circuit layer but separated by a gap. A conductive structure is forming in a second circuit layer above or below the first circuit layer, to electrically connect the first line terminal and the second line terminal.Type: GrantFiled: January 30, 2018Date of Patent: December 31, 2019Assignee: United Microelectronics Corp.Inventors: Chun-Hsien Huang, Ching-Cheng Lung, Yu-Tse Kuo, Chang-Hung Chen, Shu-Ru Wang, Wei-Chi Lee, Chun-Yen Tseng
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Publication number: 20190362776Abstract: A static random access memory (SRAM) structure includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, a second inverter comprising a second pull-up transistor and a second pull-down transistor, a first pass transistor coupled to the first inverter, and a second pass transistor coupled to the second inverter. Preferably, the first inverter is coupled to a first tunnel magnetoresistance (TMR) structure and the second inverter is coupled to a second TMR structure.Type: ApplicationFiled: June 26, 2018Publication date: November 28, 2019Inventors: Chun-Yen Tseng, Ching-Cheng Lung, Yu-Tse Kuo, Chun-Hsien Huang, Hsin-Chih Yu, Shu-Ru Wang
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Patent number: 10468420Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent PU (pull-up) FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.Type: GrantFiled: July 6, 2018Date of Patent: November 5, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hsien Huang, Yu-Tse Kuo, Shu-Ru Wang
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Memory device with oxide semiconductor static random access memory and method for operating the same
Patent number: 10410684Abstract: The present invention provides a memory device, the memory device includes a first region having a plurality of oxide semiconductor static random access memories (OSSRAM) arranged in a first direction, and each of the OSSRAMs comprising a static random access memory (SRAM) and at least an oxide semiconductor dynamic random access memory (DOSRAM), wherein the DOSRAM is connected to the SRAM, wherein each of the DOSRAMs comprises an oxide semiconductor gate (OSG), and each of the OSGs extending in a second direction perpendicular to the first direction, and an oxide semiconductor channel extending in the first direction, an oxide semiconductor gate connection extending in the first direction to connect each of the OSGs, and a word line, a Vcc connection line and a Vss connection line extend in the first direction and are connected to the SRAMs in each OSSRAM.Type: GrantFiled: February 21, 2018Date of Patent: September 10, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Yen Tseng, Ting-Hao Chang, Ching-Cheng Lung, Yu-Tse Kuo, Shih-Hao Liang, Chun-Hsien Huang, Shu-Ru Wang, Hsin-Chih Yu -
Patent number: 10366756Abstract: A control circuit for a ternary content-addressable memory includes a first logic unit and a second logic unit. The first logic unit is coupled to a first storage unit, a second storage unit, a first search line, a second search line, a reference voltage terminal, and a match line. The second logic unit is coupled to the first storage unit, the second storage unit, the first search line, the second search line, a first power supply line and a second power supply line. When voltages at the first search line and the second search line match voltages at the first storage unit and the second storage unit, the second logic unit provides a path for electrically connecting the first power supply line to the second power supply line.Type: GrantFiled: August 19, 2018Date of Patent: July 30, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Yen Tseng, Ching-Cheng Lung, Yu-Tse Kuo, Chun-Hsien Huang, Hsin-Chih Yu, Shu-Ru Wang
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MEMORY DEVICE WITH OXIDE SEMICONDUCTOR STATIC RANDOM ACCESS MEMORY AND METHOD FOR OPERATING THE SAME
Publication number: 20190221238Abstract: The present invention provides a memory device, the memory device includes a first region having a plurality of oxide semiconductor static random access memories (OSSRAM) arranged in a first direction, and each of the OSSRAMs comprising a static random access memory (SRAM) and at least an oxide semiconductor dynamic random access memory (DOSRAM), wherein the DOSRAM is connected to the SRAM, wherein each of the DOSRAMs comprises an oxide semiconductor gate (OSG), and each of the OSGs extending in a second direction perpendicular to the first direction, and an oxide semiconductor channel extending in the first direction, an oxide semiconductor gate connection extending in the first direction to connect each of the OSGs, and a word line, a Vcc connection line and a Vss connection line extend in the first direction and are connected to the SRAMs in each OSSRAM.Type: ApplicationFiled: February 21, 2018Publication date: July 18, 2019Inventors: Chun-Yen Tseng, Ting-Hao Chang, Ching-Cheng Lung, Yu-Tse Kuo, Shih-Hao Liang, Chun-Hsien Huang, Shu-Ru Wang, Hsin-Chih Yu -
Publication number: 20190206879Abstract: A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure has a first line terminal. The second circuit structure has a second line terminal. The first line terminal and the second line terminal are formed in a first circuit layer but separated by a gap. A conductive structure is forming in a second circuit layer above or below the first circuit layer, to electrically connect the first line terminal and the second line terminal.Type: ApplicationFiled: January 30, 2018Publication date: July 4, 2019Applicant: United Microelectronics Corp.Inventors: Chun-Hsien Huang, Ching-Cheng Lung, Yu-Tse Kuo, Chang-Hung Chen, Shu-Ru Wang, Wei-Chi Lee, Chun-Yen Tseng
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Publication number: 20190096892Abstract: A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise a first fin structure, the PG2A and the PG2B comprise a second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2, the first local interconnection layer and the second local interconnection layer are monolithically formed structures respectively.Type: ApplicationFiled: October 16, 2018Publication date: March 28, 2019Inventors: Shu-Ru Wang, Ching-Cheng Lung, Yu-Tse Kuo, Chien-Hung Chen, Chun-Hsien Huang, Li-Ping Huang, Chun-Yen Tseng, Meng-Ping Chuang
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Patent number: 10153287Abstract: A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise an identical first fin structure, the PG2A and the PG2B comprise an identical second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2.Type: GrantFiled: October 26, 2017Date of Patent: December 11, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shu-Ru Wang, Ching-Cheng Lung, Yu-Tse Kuo, Chien-Hung Chen, Chun-Hsien Huang, Li-Ping Huang, Chun-Yen Tseng, Meng-Ping Chuang
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Publication number: 20180315763Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent PU (pull-up) FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.Type: ApplicationFiled: July 6, 2018Publication date: November 1, 2018Inventors: Chun-Hsien Huang, Yu-Tse Kuo, Shu-Ru Wang
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Patent number: 10050046Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent PU (pull-up) FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.Type: GrantFiled: August 31, 2017Date of Patent: August 14, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hsien Huang, Yu-Tse Kuo, Shu-Ru Wang
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Patent number: 9953988Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.Type: GrantFiled: June 27, 2017Date of Patent: April 24, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hsien Huang, Yu-Tse Kuo, Shu-Ru Wang
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Patent number: 9947674Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.Type: GrantFiled: August 25, 2017Date of Patent: April 17, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hsien Huang, Yu-Tse Kuo, Shu-Ru Wang
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Patent number: 9941288Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.Type: GrantFiled: June 27, 2017Date of Patent: April 10, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hsien Huang, Yu-Tse Kuo, Shu-Ru Wang
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Publication number: 20180006040Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent PU (pull-up) FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.Type: ApplicationFiled: August 31, 2017Publication date: January 4, 2018Inventors: Chun-Hsien Huang, Yu-Tse Kuo, Shu-Ru Wang
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Patent number: 9859282Abstract: A high-density semiconductor structure includes a substrate, a bit line and a first memory unit. The bit line, disposed on the substrate, has a first side and a second side. The first memory unit includes a first transistor, a first capacitor, a second transistor and a second capacitor. The first transistor disposed on the substrate has a first terminal and a second terminal. The first terminal connects the bit line. The first capacitor connects the second terminal of the first transistor. The second transistor disposed on the substrate has a third terminal and a fourth terminal. The third terminal connects the bit line. The second capacitor connects the fourth terminal of the second transistor. The first capacitor and the second capacitor are separated from the bit line in a direction perpendicular to an extending direction of the bit line and located on the first side of the bit line.Type: GrantFiled: September 29, 2016Date of Patent: January 2, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Yen Tseng, Ching-Cheng Lung, Yu-Tse Kuo, Chun-Hsien Huang, Shu-Ru Wang