Patents by Inventor Shu-Yuan Ku
Shu-Yuan Ku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220285529Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.Type: ApplicationFiled: May 23, 2022Publication date: September 8, 2022Inventors: Ting-Gang Chen, Tai-Chun Huang, Ming-Chang Wen, Shu-Yuan Ku, Fu-Kai Yang, Tze-Liang Lee, Yung-Cheng Lu, Yi-Ting Fu
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Patent number: 11437287Abstract: A device includes a semiconductor substrate and a first gate stack over the semiconductor substrate, the first gate stack being between a first gate spacer and a second gate spacer. The device further includes a second gate stack over the semiconductor substrate between the first gate spacer and the second gate spacer and a dielectric material separating the first gate stack from the second gate stack. The dielectric material is at least partially between the first gate spacer and the second gate spacer, a first width of an upper portion of the dielectric material is greater than a second width of a lower portion of the dielectric material, and a third width of an upper portion of the first gate spacer is less than a fourth width of a lower portion of the first gate spacer.Type: GrantFiled: May 11, 2020Date of Patent: September 6, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Yao Lin, Chih-Han Lin, Shu-Uei Jang, Ya-Yi Tsai, Shu-Yuan Ku
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Publication number: 20220216201Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.Type: ApplicationFiled: March 24, 2022Publication date: July 7, 2022Inventors: Chung-Chiang Wu, Shih-Hang Chiu, Chih-Chang Hung, I-Wei Yang, Shu-Yuan Ku, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
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Publication number: 20220181217Abstract: An anchored cut-metal gate (CMG) plug, a semiconductor device including the anchored CMG plug and methods of forming the semiconductor device are disclosed herein. The method includes performing a series of etching processes to form a trench through a metal gate electrode, through an isolation region, and into a semiconductor substrate. The trench cuts-through and separates the metal gate electrode into a first metal gate and a second metal gate and forms a recess in the semiconductor substrate. Once the trench has been formed, a dielectric plug material is deposited into the trench to form a CMG plug that is anchored within the recess of the semiconductor substrate and separates the first and second metal gates. As such, the anchored CMG plug provides high levels of resistance to reduce leakage current within the semiconductor device during operation and allowing for improved V-trigger performance of the semiconductor device.Type: ApplicationFiled: February 28, 2022Publication date: June 9, 2022Inventors: Yi-Chun Chen, Ryan Chia-Jen Chen, Shu-Yuan Ku, Ya-Yi Tsai, I-Wei Yang
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Publication number: 20220173225Abstract: A method includes forming a dummy gate stack, etching the dummy gate stack to form an opening, depositing a first dielectric layer extending into the opening, and depositing a second dielectric layer on the first dielectric layer and extending into the opening. A planarization process is then performed to form a gate isolation region including the first dielectric layer and the second dielectric layer. The dummy gate stack is then removed to form trenches on opposing sides of the gate isolation region. The method further includes performing a first etching process to remove sidewall portions of the first dielectric layer, performing a second etching process to thin the second dielectric layer, and forming replacement gates in the trenches.Type: ApplicationFiled: February 14, 2022Publication date: June 2, 2022Inventors: Shih-Yao Lin, Chih-Han Lin, Shu-Uei Jang, Ya-Yi Tsai, Shu-Yuan Ku
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Patent number: 11342444Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.Type: GrantFiled: September 19, 2019Date of Patent: May 24, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Gang Chen, Tai-Chun Huang, Ming-Chang Wen, Shu-Yuan Ku, Fu-Kai Yang, Tze-Liang Lee, Yung-Cheng Lu, Yi-Ting Fu
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Publication number: 20220149181Abstract: A method includes forming a first fin and a second fin over a substrate. The method includes forming a first dummy gate structure that straddles the first fin and the second fin. The first dummy gate structure includes a first dummy gate dielectric and a first dummy gate disposed over the first dummy gate dielectric. The method includes replacing a portion of the first dummy gate with a gate isolation structure. The portion of the first dummy gate is disposed over the second fin. The method includes removing the first dummy gate. The method includes removing a first portion of the first dummy gate dielectric around the first fin, while leaving a second portion of the first dummy gate dielectric around the second fin intact. The method includes forming a gate feature straddling the first fin and the second fin, wherein the gate isolation structure intersects the gate feature.Type: ApplicationFiled: January 24, 2022Publication date: May 12, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Chih-Han Lin, Shu-Uei Jang, Ya-Yi Tsai, Chi-Hsiang Chang, Tzu-Chung Wang, Shu-Yuan Ku
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Publication number: 20220102532Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first metal gate stack and a second metal gate stack over the semiconductor substrate. The first metal gate stack and the second metal gate stack are electrically isolated from each other, and the first metal gate stack has a curved edge facing the second metal gate stack. The semiconductor device structure also includes a dielectric layer surrounding the first metal gate stack and the second metal gate stack.Type: ApplicationFiled: December 10, 2021Publication date: March 31, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Hsuan HSIAO, Shu-Yuan KU, Chih-Chang HUNG, I-Wei YANG, Chih-Ming SUN
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Patent number: 11289480Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.Type: GrantFiled: August 24, 2020Date of Patent: March 29, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Chiang Wu, Shih-Hang Chiu, Chih-Chang Hung, I-Wei Yang, Shu-Yuan Ku, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
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Publication number: 20220068720Abstract: A semiconductor device includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first and second transistors operate under a lower gate voltage than the third and fourth transistors. The first transistor has a first active gate structure and the second transistor has a second active gate structure. The first and second active gate structures are separated by a first gate isolation structure along a first direction. The third transistor has a third active gate structure and the fourth transistor has a fourth active gate structure. The third and fourth active gate structures are separated by a second gate isolation structure along the first direction. The variation of a first distance between respective sidewalls of the first gate isolation structure is equal to the variation of a second distance between respective sidewalls of the second gate isolation structure along the first direction.Type: ApplicationFiled: August 31, 2020Publication date: March 3, 2022Inventors: Shu-Uei Jang, Shu-Yuan Ku, Shih-Yao Lin
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Patent number: 11264287Abstract: An anchored cut-metal gate (CMG) plug, a semiconductor device including the anchored CMG plug and methods of forming the semiconductor device are disclosed herein. The method includes performing a series of etching processes to form a trench through a metal gate electrode, through an isolation region, and into a semiconductor substrate. The trench cuts-through and separates the metal gate electrode into a first metal gate and a second metal gate and forms a recess in the semiconductor substrate. Once the trench has been formed, a dielectric plug material is deposited into the trench to form a CMG plug that is anchored within the recess of the semiconductor substrate and separates the first and second metal gates. As such, the anchored CMG plug provides high levels of resistance to reduce leakage current within the semiconductor device during operation and allowing for improved V-trigger performance of the semiconductor device.Type: GrantFiled: February 11, 2020Date of Patent: March 1, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Chun Chen, Ryan Chia-Jen Chen, Shu-Yuan Ku, Ya-Yi Tsai, I-Wei Yang
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Patent number: 11251284Abstract: A method includes forming a dummy gate stack, etching the dummy gate stack to form an opening, depositing a first dielectric layer extending into the opening, and depositing a second dielectric layer on the first dielectric layer and extending into the opening. A planarization process is then performed to form a gate isolation region including the first dielectric layer and the second dielectric layer. The dummy gate stack is then removed to form trenches on opposing sides of the gate isolation region. The method further includes performing a first etching process to remove sidewall portions of the first dielectric layer, performing a second etching process to thin the second dielectric layer, and forming replacement gates in the trenches.Type: GrantFiled: May 6, 2020Date of Patent: February 15, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Chih-Han Lin, Shu-Uei Jang, Ya-Yi Tsai, Shu-Yuan Ku
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Publication number: 20220037196Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.Type: ApplicationFiled: October 14, 2021Publication date: February 3, 2022Inventors: Shu-Yuan Ku, Chih-Ming Sun, Chun-Fai Cheng
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Patent number: 11233139Abstract: A method includes forming a first fin and a second fin over a substrate. The method includes forming a first dummy gate structure that straddles the first fin and the second fin. The first dummy gate structure includes a first dummy gate dielectric and a first dummy gate disposed over the first dummy gate dielectric. The method includes replacing a portion of the first dummy gate with a gate isolation structure. The portion of the first dummy gate is disposed over the second fin. The method includes removing the first dummy gate. The method includes removing a first portion of the first dummy gate dielectric around the first fin, while leaving a second portion of the first dummy gate dielectric around the second fin intact. The method includes forming a gate feature straddling the first fin and the second fin, wherein the gate isolation structure intersects the gate feature.Type: GrantFiled: June 26, 2020Date of Patent: January 25, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Shih-Yao Lin, Chih-Han Lin, Shu-Yuan Ku, Tzu-Chung Wang, Shu-Uei Jang, Ya-Yi Tsai, Chi-Hsiang Chang
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Publication number: 20210408263Abstract: A method includes forming a first fin and a second fin over a substrate. The method includes forming a first dummy gate structure that straddles the first fin and the second fin. The first dummy gate structure includes a first dummy gate dielectric and a first dummy gate disposed over the first dummy gate dielectric. The method includes replacing a portion of the first dummy gate with a gate isolation structure. The portion of the first dummy gate is disposed over the second fin. The method includes removing the first dummy gate. The method includes removing a first portion of the first dummy gate dielectric around the first fin, while leaving a second portion of the first dummy gate dielectric around the second fin intact. The method includes forming a gate feature straddling the first fin and the second fin, wherein the gate isolation structure intersects the gate feature.Type: ApplicationFiled: June 26, 2020Publication date: December 30, 2021Inventors: Shih-Yao Lin, Chih-Han Lin, Shu-Yuan Ku, Tzu-Chung Wang, Shu-Uei Jang, Ya-Yi Tsai, Chi-Hsiang Chang
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Patent number: 11201230Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first metal gate stack and a second metal gate stack over a semiconductor substrate. The semiconductor device structure also includes a dielectric layer surrounding the first metal gate stack and the second metal gate stack. The semiconductor device structure further includes an insulating structure between the first metal gate stack and the second metal gate stack. The insulating structure has a first convex surface facing towards the first metal gate stack.Type: GrantFiled: October 22, 2019Date of Patent: December 14, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Hsuan Hsiao, Shu-Yuan Ku, Chih-Chang Hung, I-Wei Yang, Chih-Ming Sun
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Publication number: 20210335674Abstract: A semiconductor device includes a first semiconductor fin extending along a first direction. The semiconductor device includes a second semiconductor fin also extending along the first direction. The semiconductor device includes a dielectric structure disposed between the first and second semiconductor fins. The semiconductor device includes a gate isolation structure vertically disposed above the dielectric structure. The semiconductor device includes a metal gate layer extending along a second direction perpendicular to the first direction, wherein the metal gate layer includes a first portion straddling the first semiconductor fin and a second portion straddling the second semiconductor fin. The gate isolation structure separates the first and second portions of the metal gate layer from each other and includes a bottom portion extending into the dielectric structure.Type: ApplicationFiled: February 3, 2021Publication date: October 28, 2021Applicant: Taiwan Semicondutor Manufacturing Company LimitedInventors: Shih-Yao Lin, Chih-Han Lin, Shu-Yuan Ku, Shu-Uei Jang, Ya-Yi Tsai, I-Wei Yang
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Patent number: 11152250Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.Type: GrantFiled: June 25, 2020Date of Patent: October 19, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shu-Yuan Ku, Chih-Ming Sun, Chun-Fai Cheng
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Patent number: 11145536Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.Type: GrantFiled: December 10, 2019Date of Patent: October 12, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shu-Yuan Ku, Chih-Ming Sun, Chun-Fai Cheng
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Publication number: 20210296181Abstract: The first and second fins extend upwardly from a semiconductor substrate. The shallow trench isolation structure laterally surrounds lower portions of the first and second fins. The first gate structure extends across an upper portion of the first fin. The second gate structure extends across an upper portion of the second fin. The first source/drain epitaxial structures are on the first fin and on opposite sides of the first gate structure. The second source/drain epitaxial structures are on the second fin and on opposite sides of the second gate structure. The separation plug interposes the first and second gate structures and extends along a lengthwise direction of the first fin. The isolation material cups an underside of a portion of the separation plug between one of the first source/drain epitaxial structures and one of the second source/drain epitaxial structures.Type: ApplicationFiled: June 7, 2021Publication date: September 23, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Chang HUNG, Shu-Yuan KU, I-Wei YANG, Yi-Hsuan HSIAO, Ming-Ching CHANG, Ryan Chia-Jen CHEN