Patents by Inventor Shuang Meng

Shuang Meng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180286693
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Application
    Filed: May 30, 2018
    Publication date: October 4, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Publication number: 20180261503
    Abstract: The disclosure relates to a method of making molybdenum films utilizing boron and molybdenum nucleation layers. The resulting molybdenum films have low electrical resistivity, are substantially free of boron, and can be made at reduced temperatures compared to conventional chemical vapor deposition processes that do not use the boron or molybdenum nucleation layers. The molybdenum nucleation layer formed by this process can protect the substrate from the etching effect of MoCl5 or MoOCl4, facilitates nucleation of subsequent CVD Mo growth on top of the molybdenum nucleation layer, and enables Mo CVD deposition at lower temperatures. The nucleation layer can also be used to control the grain sizes of the subsequent CVD Mo growth, and therefore controls the electrical resistivity of the Mo film.
    Type: Application
    Filed: April 20, 2018
    Publication date: September 13, 2018
    Inventors: Shuang Meng, Richard Ulrich Assion, Thomas H. Baum, Bryan Clark Hendrix
  • Publication number: 20180142345
    Abstract: The disclosure relates to a method of making molybdenum films utilizing boron and molybdenum nucleation layers. The resulting molybdenum films have low electrical resistivity, are substantially free of boron, and can be made at reduced temperatures compared to conventional chemical vapor deposition processes that do not use the boron or molybdenum nucleation layers. The molybdenum nucleation layer formed by this process can protect the substrate from the etching effect of MoCl5 or MoOCl4, facilitates nucleation of subsequent CVD Mo growth on top of the molybdenum nucleation layer, and enables Mo CVD deposition at lower temperatures. The nucleation layer can also be used to control the grain sizes of the subsequent CVD Mo growth, and therefore controls the electrical resistivity of the Mo film.
    Type: Application
    Filed: November 22, 2017
    Publication date: May 24, 2018
    Inventors: Shuang Meng, Richard Ulrich Assion, Thomas H. Baum, Bryan Clark Hendrix
  • Publication number: 20180019165
    Abstract: A method of forming a molybdenum-containing material on a substrate is described, in which the substrate is contacted with molybdenum oxytetrachloride (MoOCl4) vapor under vapor deposition conditions, to deposit the molybdenum-containing material on the substrate. In various implementations, a diborane contact of the substrate may be employed to establish favorable nucleation conditions for the subsequent bulk deposition of molybdenum, e.g., by chemical vapor deposition (CVD) techniques such as pulsed CVD.
    Type: Application
    Filed: July 13, 2017
    Publication date: January 18, 2018
    Inventors: Thomas H. Baum, Philip S.H. Chen, Robert Wright, Bryan Hendrix, Shuang Meng, Richard Assion
  • Publication number: 20170372913
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Application
    Filed: August 18, 2017
    Publication date: December 28, 2017
    Applicant: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Patent number: 9761457
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: September 12, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Publication number: 20160203993
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Application
    Filed: March 21, 2016
    Publication date: July 14, 2016
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Patent number: 9305782
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: April 5, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greely, Brian J. Coppa
  • Publication number: 20150021744
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Application
    Filed: October 6, 2014
    Publication date: January 22, 2015
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greely, Brian J. Coppa
  • Publication number: 20150001673
    Abstract: A transition metal oxide dielectric material is doped with a non-metal in order to enhance the electrical properties of the metal oxide. In a preferred embodiment, a transition metal oxide is deposited over a bottom electrode and implanted with a dopant. In a preferred embodiment, the metal oxide is hafnium oxide or zirconium oxide and the dopant is nitrogen. The dopant can convert the crystal structure of the hafnium oxide or zirconium oxide to a tetragonal structure and increase the dielectric constant of the metal oxide.
    Type: Application
    Filed: July 7, 2014
    Publication date: January 1, 2015
    Inventors: Jiutao Li, Shuang Meng
  • Patent number: 8852851
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: October 7, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph N. Greeley, Brian J. Coppa
  • Patent number: 8816447
    Abstract: Devices such as transistors having an oxide layer that provide a depletion field in a conduction channel. A barrier layer is formed over the oxide layer. A gate electrode is formed over the barrier layer. The barrier layer and gate electrode are configured to reduce the width of the depletion field absent a voltage applied to the gate electrode.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: August 26, 2014
    Assignee: Round Rock Research, LLC
    Inventors: Shuang Meng, Garo J. Derderian, Gurtej S. Sandhu
  • Patent number: 8791519
    Abstract: A transition metal oxide dielectric material is doped with a non-metal in order to enhance the electrical properties of the metal oxide. In a preferred embodiment, a transition metal oxide is deposited over a bottom electrode and implanted with a dopant. In a preferred embodiment, the metal oxide is hafnium oxide or zirconium oxide and the dopant is nitrogen. The dopant can convert the crystal structure of the hafnium oxide or zirconium oxide to a tetragonal structure and increase the dielectric constant of the metal oxide.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: July 29, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Jiutao Li, Shuang Meng
  • Publication number: 20140083453
    Abstract: A method for in situ cleaning of a Metal-Organic Chemical Vapor Deposition reaction chamber is provided in embodiments of the present invention. The method includes: introducing a first cleaning gas into the reaction chamber, converting the first cleaning gas into first plasma inside the reaction chamber to completely remove a carbonaceous organic substance inside the reaction chamber, wherein the first cleaning gas includes a first oxygen-containing gas; and introducing a second cleaning gas into the reaction chamber, and converting the second cleaning gas into second plasma inside the reaction chamber to completely remove a metallic oxide inside the reaction chamber, wherein the second cleaning gas includes a first halogen-containing gas.
    Type: Application
    Filed: September 19, 2013
    Publication date: March 27, 2014
    Applicant: Advanced Micro-Fabrication Equipment Inc, Shanghai
    Inventors: Gerald Zheyao Yin, Zhiyou Du, Shuang Meng, Yang Wang, Ying Zhang, Songlin Xu, Ban Zhu, Haruhisa Takiguchi
  • Publication number: 20140083452
    Abstract: The present invention provides a method for in situ cleaning of an MOCVD reaction chamber. The method includes: maintaining the internal pressure of the MOCVD reaction chamber in a predetermined pressure range, and keeping a plasma inside the MOCVD reaction chamber for a predetermined time period to completely remove deposits inside the MOCVD reaction chamber. The method for in situ cleaning of an MOCVD reaction chamber according to the embodiments of the present invention may remove relatively stable organic ligands or related polymers, resulting in a good cleaning effect for the removal of the deposits on the surfaces with a relatively low temperature inside the MOCVD reaction chamber.
    Type: Application
    Filed: September 19, 2013
    Publication date: March 27, 2014
    Applicant: Advanced Micro-Fabrication Equipment Inc, Shanghai
    Inventors: Gerald Zheyao Yin, Zhiyou Du, Shuang Meng, Yang Wang, Ying Zhang
  • Publication number: 20140083451
    Abstract: The present invention provides a method for in situ cleaning of an MOCVD reaction chamber. The method includes: introducing a first cleaning gas into the reaction chamber, and converting the first cleaning gas into a first plasma inside the reaction chamber, and maintaining the pressure inside the reaction chamber in a first predetermined pressure range for a first time period, to remove a carbonaceous organic substance inside the reaction chamber; introducing a second cleaning gas into the reaction chamber, and converting the second cleaning gas into second plasma inside the reaction chamber, and maintaining the pressure inside the reaction chamber in a second predetermined pressure range for a second time period, to remove metal and its compound inside the reaction chamber.
    Type: Application
    Filed: September 19, 2013
    Publication date: March 27, 2014
    Applicant: Advanced Micro-Fabrication Equipment Inc, Shanghai
    Inventors: Gerald Zheyao Yin, Zhiyou Du, Shuang Meng, Yang Wang, Ying Zhang
  • Patent number: 8598632
    Abstract: An integrated circuit having differently-sized features wherein the smaller features have a pitch multiplied relationship with the larger features, which are of such size as to be formed by conventional lithography.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: December 3, 2013
    Assignee: Round Rock Research LLC
    Inventors: Luan Tran, William T. Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi Bai, Zhiping Yin, Paul Morgan, Mirzafer K. Abatchev, Gurtej S. Sandhu, D. Mark Durcan
  • Patent number: 8362576
    Abstract: Atomic layer deposition is enhanced using plasma. Plasma begins prior to flowing a second precursor into a chamber. The second precursor reacts with a first precursor to deposit a layer on a substrate. The layer may include at least one element from each of the first and second precursors. The layer may be TaN, and the precursors may be TaF5 and NH3. The plasma may begin during purge gas flow between a pulse of the first precursor and a pulse of the second precursor. Thermal energy assists the reaction of the precursors to deposit the layer on the substrate. The thermal energy may be greater than generally accepted for ALD (e.g., more than 300 degrees Celsius).
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: January 29, 2013
    Assignee: Round Rock Research, LLC
    Inventors: Shuang Meng, Garo J. Derderian, Gurtej S. Sandhu
  • Publication number: 20120256309
    Abstract: An integrated circuit having differently-sized features wherein the smaller features have a pitch multiplied relationship with the larger features, which are of such size as to be formed by conventional lithography.
    Type: Application
    Filed: June 22, 2012
    Publication date: October 11, 2012
    Inventors: Luan Tran, William T. Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi (Jenny) Bai, Zhiping Yin, Paul Morgan, Mirzafer K. Abatchev, Gurtej S. Sandhu, D. Mark Durcan
  • Patent number: 8257497
    Abstract: Systems and methods for insitu post atomic layer deposition (ALD) destruction of active species are provided. ALD processes deposit multiple atomic layers on a substrate. Pre-cursor gases typically enter a reactor and react with the substrate resulting in a monolayer of atoms. After the remaining gas is purged from the reactor, a second pre-cursor gas enters the reactor and the process is repeated. The active species of some pre-cursor gases do not readily purge from the reactor, thus increasing purge time and decreasing throughput. A high-temperature surface placed in the reactor downstream from the substrate substantially destroys the active species insitu. Substantially destroying the active species allows the reactor to be readily purged, increasing throughput.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: September 4, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Demetrius Sarigiannis, Shuang Meng, Garo J Derderian