Patents by Inventor Shubneesh Batra
Shubneesh Batra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220208996Abstract: Methods and apparatus for processing a substrate are provided herein. For example, a method can include depositing a first metal layer on a substrate and etching the first metal layer to form a gate electrode, depositing a dielectric layer atop the gate electrode, depositing a semi-conductive oxide layer atop the dielectric layer to cover a portion of the gate electrode, etching the dielectric layer from a portion of the gate electrode that is not covered by the semi-conductive oxide layer to form a gate access via, and depositing a second metal layer atop the dielectric layer and the semi-conductive oxide layer, and within the gate access via.Type: ApplicationFiled: December 31, 2020Publication date: June 30, 2022Inventors: Shubneesh BATRA, Guan Huei SEE
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Patent number: 8541821Abstract: The invention provides a method of forming an electron memory storage device and the resulting device. The device comprises a gate structure which, in form, comprises a first gate insulating layer formed over a semiconductor substrate, a self-forming electron trapping layer of noble metal nano-crystals formed over the first gate insulating layer, a second gate insulating layer formed over the electron trapping layer, a gate electrode formed over the second gate insulating layer, and source and drain regions formed on opposite sides of the gate structure.Type: GrantFiled: September 16, 2011Date of Patent: September 24, 2013Assignee: Micron Technology, Inc.Inventors: Shubneesh Batra, Gurtej Sandhu
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Publication number: 20120028429Abstract: The invention provides a method of forming an electron memory storage device and the resulting device. The device comprises a gate structure which, in form, comprises a first gate insulating layer formed over a semiconductor substrate, a self-forming electron trapping layer of noble metal nano-crystals formed over the first gate insulating layer, a second gate insulating layer formed over the electron trapping layer, a gate electrode formed over the second gate insulating layer, and source and drain regions formed on opposite sides of the gate structure.Type: ApplicationFiled: September 16, 2011Publication date: February 2, 2012Inventors: Shubneesh Batra, Gurtej Sandhu
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Patent number: 7939394Abstract: Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.Type: GrantFiled: March 28, 2008Date of Patent: May 10, 2011Assignee: Micron Technology, Inc.Inventors: Shubneesh Batra, Howard C. Kirsch, Gurtej S. Sandhu, Xianfeng Zhou, Chih-Chen Cho
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Publication number: 20110024762Abstract: A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing.Type: ApplicationFiled: October 11, 2010Publication date: February 3, 2011Applicant: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Shubneesh Batra, Pierre C. Fazan
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Patent number: 7825414Abstract: A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing.Type: GrantFiled: October 24, 2008Date of Patent: November 2, 2010Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Shubneesh Batra, Pierre C. Fazan
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Publication number: 20090302322Abstract: A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing.Type: ApplicationFiled: June 26, 2009Publication date: December 10, 2009Applicant: MICRON TECHNOLOGY, INC.Inventors: Gurtej S. Sandhu, Shubneesh Batra, Pierre C. Fazan
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Patent number: 7566907Abstract: A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing.Type: GrantFiled: June 9, 2008Date of Patent: July 28, 2009Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Shubneesh Batra, Pierre C. Fazan
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Publication number: 20090047776Abstract: A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing.Type: ApplicationFiled: October 24, 2008Publication date: February 19, 2009Applicant: MICRON TECHNOLOGY, INC.Inventors: Gurtej S. Sandhu, Shubneesh Batra, Pierre C. Fazan
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Patent number: 7452760Abstract: A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing.Type: GrantFiled: December 21, 2006Date of Patent: November 18, 2008Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Shubneesh Batra, Pierre C. Fazan
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Publication number: 20080237601Abstract: A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing.Type: ApplicationFiled: June 9, 2008Publication date: October 2, 2008Inventors: Gurtej S. Sandhu, Shubneesh Batra, Pierre C. Fazan
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Publication number: 20080176378Abstract: Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.Type: ApplicationFiled: March 28, 2008Publication date: July 24, 2008Inventors: Shubneesh Batra, Howard C. Kirsch, Gurtej S. Sandhu, Xianfeng Zhou, Chih-Chen Cho
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Patent number: 7385222Abstract: A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing.Type: GrantFiled: December 22, 2004Date of Patent: June 10, 2008Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Shubneesh Batra, Pierre C. Fazan
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Patent number: 7354812Abstract: Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.Type: GrantFiled: September 1, 2004Date of Patent: April 8, 2008Assignee: Micron Technology, Inc.Inventors: Shubneesh Batra, Howard C. Kirsch, Gurtej S. Sandhu, Xianfeng Zhou, Chih-Chen Cho
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Patent number: 7259464Abstract: An interconnection array subunit and method for forming the interconnection array subunit are provided, the interconnection array subunit including a first pair of line conductors in first and second regions, the first pair of line conductors including a first true line conductor and a first associated complementary line conductor connected and vertically twisted in a vertical twisting region between the first and second regions. The interconnection array subunit also includes a second pair of line conductors adjacent to the first pair of line conductors in the first and second regions, the second pair of line conductors including a second true line conductor and a second associated complementary line conductor.Type: GrantFiled: May 9, 2000Date of Patent: August 21, 2007Assignee: Micron Technology, Inc.Inventor: Shubneesh Batra
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Publication number: 20070102705Abstract: A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing.Type: ApplicationFiled: December 21, 2006Publication date: May 10, 2007Inventors: Gurtej Sandhu, Shubneesh Batra, Pierre Fazan
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Publication number: 20070050743Abstract: An interconnection array subunit and method for forming the interconnection array subunit are provided, the interconnection array subunit including a first pair of line conductors in first and second regions, the first pair of line conductors including a first true line conductor and a first associated complementary line conductor connected and vertically twisted in a vertical twisting region between the first and second regions. The interconnection array subunit also includes a second pair of line conductors adjacent to the first pair of line conductors in the first and second regions, the second pair of line conductors including a second true line conductor and a second associated complementary line conductor.Type: ApplicationFiled: October 2, 2006Publication date: March 1, 2007Applicant: Micron Technology, Inc.Inventor: Shubneesh Batra
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Patent number: 7160795Abstract: A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels is described. The method comprises forming a bond pad at least partially exposed at the top surface of the integrated circuit, forming a metal pad on the metal level below the bond pad and forming an underlying metal pad on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads to the area of the bond pad is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.Type: GrantFiled: November 12, 2002Date of Patent: January 9, 2007Assignee: Micron Technology, Inc.Inventors: Shubneesh Batra, Michael D. Chaine, Brent Keeth, Salman Akram, Troy A. Manning, Brian Johnson, Chris G. Martin, Todd A. Merritt, Eric J. Smith
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Patent number: 7071534Abstract: An antifuse structure and method of use are disclosed. According to one embodiment of the present invention a first programming voltage is coupled to a well of a first conductivity type in a substrate of a second conductivity type in an antifuse. A second programming voltage is coupled to a conductive terminal of the second conductivity type in the antifuse to create a current path through an insulator between the conductive terminal and the well to program the antifuse. The first programming voltage may be coupled to an ohmic contact in the well in the antifuse.Type: GrantFiled: September 1, 2004Date of Patent: July 4, 2006Assignee: Micron Technology, Inc.Inventors: Kenneth W. Marr, Shubneesh Batra
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Patent number: 7041547Abstract: In one aspect, the invention encompasses a method of forming a polished material. A substrate is provided and an elevational step is provided relative to the substrate. The elevational step has an uppermost surface. A material is formed beside the elevational step. The material extends to above the elevational step uppermost surface and has lower and upper layers. The lower layer polishes at slower rate than the upper layer under common polishing conditions. The lower layer joins the upper layer at an interface. The material is polished down to about the elevational level of the elevational step uppermost surface utilizing the common polishing conditions. In another aspect, the invention encompasses a method of forming an isolation region. A substrate is provided. The substrate has an opening extending therein and a surface proximate the opening. A material is formed within the opening. The material extends to above the substrate surface, and comprises a lower layer and an upper layer.Type: GrantFiled: January 31, 2005Date of Patent: May 9, 2006Assignee: Micron Technology, Inc.Inventors: Shubneesh Batra, Gurtej S. Sandhu