Vertical Twist Scheme for High Density DRAMs
An interconnection array subunit and method for forming the interconnection array subunit are provided, the interconnection array subunit including a first pair of line conductors in first and second regions, the first pair of line conductors including a first true line conductor and a first associated complementary line conductor connected and vertically twisted in a vertical twisting region between the first and second regions. The interconnection array subunit also includes a second pair of line conductors adjacent to the first pair of line conductors in the first and second regions, the second pair of line conductors including a second true line conductor and a second associated complementary line conductor. The interconnection array subunit also includes a first interconnection layer disposed in the vertical twisting region, the first interconnection layer connecting the second associated complementary line conductor in the first region to the second associated complementary line conductor in the second region. The interconnection array subunit also includes a second interconnection layer disposed in the vertical twisting region, the second interconnection layer connecting the second true line conductor in the first region to the second true line conductor in the second region. The first true line conductor is disposed below the first associated complementary line conductor in the first region and above the first associated complementary line conductor in the second region. The second true line conductor is disposed below the second associated complementary line conductor in the first and second regions.
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This application is a divisional of U.S. patent application Ser. No. 09/567,673, filed May 9, 2000, which is incorporated herein by reference in its entirety and to which priority is claimed.
FIELD OF THE INVENTIONThis invention relates generally to a semiconductor memory array and semiconductor integrated circuits, and, more particularly to a scheme for arranging line conductors and interconnection lines in such a semiconductor memory array and in semiconductor integrated circuits.
BACKGROUND OF THE INVENTIONSemiconductor integrated circuits (ICs) typically are formed by metal-oxide semiconductor (MOS) or bipolar transistors that are integrated at a planar major surface of a silicon chip. Electrical interconnections between various transistors, and between certain transistors and input/output pads, have taken the form of electrically connecting lines that comprise a layer of metallization running along an essentially planar surface. In some ICs, two or more “levels” of interconnections may be required. The planar surfaces of the interconnections are oriented mutually parallel to, and are insulated from, both each other and the top planar surface of the chip by suitable insulating layers. Connections to the transistors at lower levels than the metallization layers are provided through openings called contacts, and connections between different interconnection layers are provided through insulation openings called vias.
In memory ICs, such as random access memories (RAMs), the data in the memory array are accessed by an external data path by means of a number of electrically conducting lines. The electrically conducting lines in the array are conventionally arranged in the form of an array of parallel metallization strips. For example, a dynamic RAM (DRAM) contains an array of hundreds of parallel bit lines, or digit lines. A DRAM also contains an array of parallel word lines. The word lines typically lie at a different planar level than the bit lines. The array of bit lines and the array of word lines lie perpendicular to each other, forming a grid. Memory cells in the DRAM lie at an intersection of a bit line and a word line.
The bit lines, or digit lines, in a DRAM can give rise to electrical cross-coupling or “cross-talk.” For example, access to any given bit line or digit line may spuriously influence memory cells connected to adjacent bit lines or digit lines. The term “pattern sensitivity” is applied to this undesirable phenomenon. The problems of cross-talk and pattern sensitivity can arise in other interconnection arrays, such as address busses and data busses where similarly paired, parallelly disposed line conductors are employed. In these environments, cross-talk and pattern sensitivity can result in undesirable errors.
Memory ICs such as DRAMs typically have a memory array of millions of memory cells that store electrical charges indicative of binary data. For instance, the presence of an electrical charge in the memory cell usually equates to a binary “1” value, and the absence of an electrical charge usually equates to a binary “0” value. The memory cells are accessed via address signals on row and column lines. Once accessed, data is written to, or read from, the addressed memory cell via bit lines, or digit lines.
One common design found in many memory circuit topologies or configurations or layouts is the “folded bit line” or “folded digit line” structure or architecture, also known as the 8F2 architecture. In a folded bit line construction, the bit lines are arranged in pairs with each pair being assigned to complementary binary signals. For example, one bit line (the “true” line) in the pair is dedicated to a binary signal DATA while the other bit line (the “associated complementary” line) in the pair is dedicated to handle the associated complementary binary signal DATA*. (The asterisk notation “*” is used throughout to indicate the binary complement.)
The memory cells are connected to one of the bit lines in the folded pair. During read and write operations, the bit lines are driven to opposing voltage levels depending on the data content being written to or read from the memory cell. For purposes of explanation, the following example describes a read operation of a memory cell holding a charge indicative of a binary “1” value. The voltage potential of both bit lines in the pair are first preferably equalized to a middle voltage level such as 1.2V for a memory circuit with a supply voltage level of 2.5V. Then, the addressed memory cell is accessed and the charge held therein begins to flow to one of the bit lines in the bit line pair, causing the voltage of that bit line to be raised slightly above the voltage of the other bit line of the pair. A sense amplifier, or similar circuit, senses the voltage differential on the bit line pair and further increases this differential by increasing the voltage on the first bit line to 2.5V and decreasing the voltage on the second bit line to 0 V. The folded bit lines thereby output the data in a complementary form, which is transmitted to the output pads.
One version of a folded bit line architecture or structure is the twisted bit line structure.
Conventional twisted bit line architectures have a number of disadvantages as compared to open bit line architectures. One disadvantage is the relatively large amount of chip “real estate” that is typically used by the twist junctions 120. Yet another disadvantage is that the use of the conventional twisted folded bit line architecture may result in an inefficient use of the cell matrix space. The conventional twisted bit line architecture does not use space efficiently because it provides a lower packing density of memory cells than the open bit line architecture, and because it cannot utilize a cross-point layout cell structure. Some of these disadvantages could be overcome if a cross-point layout were combined with a folded bit line architecture. This combination would offer both high packing density and good noise immunity. Implementing this combination would require that the bit lines be vertically twisted, not just horizontally twisted as shown in
One attempt in the prior art to provide a DRAM architecture that utilizes the advantages of both a cross-point layout cell architecture and a folded bit line architecture is described in U.S. Pat. No. 5,107,459 to Chu et al. Chu utilizes a three-dimensional approach by stacking the two lines in a bit line pair (the true bit line and the complementary bit line) vertically one above the other in two layers of metallization. The two layers are twisted by means of a third layer.
A scheme similar to the scheme described by Chu is shown conceptually and schematically in
In the scheme shown in
Vertical twisting of the other bit line pair (D1, D1*) in sub-array 200 is accomplished in a different manner. The portion of the true bit line D1 on the left of the twisting region 210 (DIL) is formed in the first (lower) layer of metallization, while the portion of D1 on the right of the twisting region 210 (DIR) is formed in the second (upper) layer of metallization. Likewise, the portion of the complementary bit line D1* on the left of the twisting region 210 (D1L*) is formed in the second (upper) layer of metallization, while the portion of D1* on the right of the twisting region 210 (D1R*) is formed in the first (lower) layer of metallization. As shown in
The vertical twisting scheme represented in
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the perceived shortcomings of prior art twisting schemes. Furthermore, the present invention advantageously occupies less chip “real estate” than the vertical twisting scheme represented in
In accordance with one aspect of the present invention, an interconnection array subunit and method for forming the interconnection array subunit are provided, the interconnection array subunit including a first pair of line conductors in first and second regions, the first pair of line conductors including a first true line conductor and a first associated complementary line conductor connected and vertically twisted in a vertical twisting region between the first and second regions. The interconnection array subunit also includes a second pair of line conductors adjacent to the first pair of line conductors in the first and second regions, the second pair of line conductors including a second true line conductor and a second associated complementary line conductor. The interconnection array subunit also includes a first interconnection layer disposed in the vertical twisting region, the first interconnection layer connecting the second associated complementary line conductor in the first region to the second associated complementary line conductor in the second region. The interconnection array subunit also includes a second interconnection layer disposed in the vertical twisting region, the second interconnection layer connecting the second true line conductor in the first region to the second true line conductor in the second region. The two interconnection layers do so by bypassing beneath the adjacent twist region. The first true line conductor is disposed below the first associated complementary line conductor in the first region and above the first associated complementary line conductor in the second region. The second true line conductor is disposed below the second associated complementary line conductor in the first and second regions.
In accordance with another aspect of the instant invention, a method is provided for laying out line conductors for such an interconnection array subunit.
BRIEF DESCRIPTION OF THE DRAWINGSOther objects and advantages of the invention will become apparent upon reading the following detailed description of a specific embodiment of the invention, and upon reference to the accompanying drawings, in which:
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
DETAILED DESCRIPTIONIllustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, that will vary from one implementation to another. Moreover, it will be appreciated that such a development effort, even if complex and time-consuming, would be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
Turning now to the drawings, and in particular to
The interconnection array also contains a vertical twisting region 310, which is situated between two dummy word lines 320. The interconnection array can be considered to consist of three regions: the region to the left of the twisting region 310, the twisting region 310, and the region to the right of the twisting region 310. The portions of the digit lines in each digit line pair, (Di, Di*) (with i=1, 2, . . . 8), in the region to the left of the twisting region 310 are designated DiL and DiL*, while the portions of the digit lines in the region to the right of the twisting region 310 are designated DiR and DiR*. The digit lines within each digit line pair are separated by a digit line pitch P.
In the embodiment in
The alternating dashed-dotted lines of
In the interconnection array shown in
The vertical twisting of the odd digit line pairs (D2j+1, D2j+1*) (j=0, 1, 2, 3, 4) is effected in the vertical twisting region 310 by having the true odd digit lines, D2j+1L (j=0, 1, 2, 3, 4), connect to their respective true odd digit lines to the right of the twisting region 310, D2j+1R (j=0, 1, 2, 3, 4), through contact holes 330 and 340. As shown in
The vertical twisting of the odd digit line pairs is further effected by having the associated complementary digit lines in the region to the left of the twisting region 310, D2j+1L* (j=0, 1, 2, 3, 4), connect to their respective associated complementary digit lines in the region to the right of the twisting region, D2j+1R* (j=0, 1, 2, 3, 4). This connection takes place through contact holes 340, as shown in
In contrast to the odd-numbered digit lines pairs, the even-numbered digit line pairs (D2k, D2k*) (k=1, 2, 3, 4) are not vertically twisted within the vertical twisting region 310. As shown in
As shown in
As shown in
In the interconnection array in
The vertical twisting scheme implemented in the interconnection array in
In
In the physical layout shown in
Turning now to
The insulating layer 510 also insulates the dummy word lines 320 and the interconnection 350 from the true digit line D5L and the associated complementary digit line D5R*, both formed in the buried layer of polycide. The insulating layer 520 insulates the true digit line D5L and the associated complementary digit line D5R*, both formed in the buried layer of polycide, from the associated complementary digit line D5L* and the true digit line D5R, both formed in the layer of metallization. The true digit line D5L connects to the respective true digit line D5R through the contact hole 330, which is surrounded by the surround 430. A suitable plug, such as an aluminum plug or a tungsten plug, may be used to fill the contact hole 330.
The polysilicon interconnection layer 350 connects, in turn, to the corresponding associated complementary digit line D8R* through the contact hole 360, which is surrounded by the surround 460. A suitable plug, such as an aluminum or a tungsten plug, may be used to fill the contact holes 355 and 360. Also shown in
The fabrication of embodiments of the present invention involve a number of process steps. These steps are typically inherent to a DRAM process and no special steps are required except in some cases. A first step includes forming a p-well in a semiconductor substrate such as a silicon substrate, which will hold the DRAM array. A second step includes forming active areas and field isolation regions. A third step includes forming n-well regions in which the p-channel devices will be formed. A fourth step includes forming a first insulating layer on the active areas to act as gate oxide layers for transfer transistors. A fifth step includes forming and patterning a polysilicon/tungsten silicide/cap oxide stack (also referred to as polysilicon or poly) on the first insulating layer to act as gate electrodes for the transfer transistors, word lines and also form interconnections 350 in the vertical twisting region 310.
Next, sidewall spacers are formed on the polysilicon gates, and the n-channel and p-channel transistors are formed by masking and implantation according to the CMOS process employed. A barrier oxide layer (300 A or so) is then deposited followed by Borophosphsilicate glass (BPSG) deposition. This is planarized, using, for example, chemical-mechanical polishing (CMP) techniques known to those of ordinary skill in the art to provide a planarized surface for subsequent processing. Contact holes are then formed in the BPSG layers, these holes then being filled with conductive plugs of, for example, heavily n-type polysilicon. These plugs are used in the array to contact the cell capacitors and in the twist region to form contacts between the buried digit line and active area. They could also be employed to contact the n-channel transistors in the periphery.
The next step involves deposition of a thin (e.g., 500 Å) oxide (TEOS) layer, and patterning that layer using conventional mask techniques to open up holes therein through to the plugs desired to be contacted, including those in the twist where a contact between the buried digit line and active area needs to be formed
Another polysilicon/tungsten silicide/cap oxide stack is deposited and patterned to form the buried digit lines. After this is accomplished, the DRAM capacitors are formed on top of the digit lines, in a conventional manner.
After capacitor formation, another layer of BPSG is deposited and planarized as previously described. The BPSG layer is then patterned to form contacts to active areas, polysilicon plugs or buried digit lines below, including contacts in the twist region where the buried digit line is to be twisted up to metal 1 and metal 1 twisted down to buried digit line. The contacts are then filled with plugs of, for example, tungsten after a barrier layer such as TiN has been deposited. Chemical Vapor Deposition (CVD) is typically used for these steps. Next the metal 1 is formed and patterned. The metal 1 in a typical embodiment comprises a 300 A Ti/3 kA AlCu/300 A TiN stack. It is used to form interconnects for the circuits, route power supplies and form the complementary digit lines. At this point, the processing completes the formation of the vertical twist. The remaining steps such as metal 2, passivation etc. in the DRAM processing can be carried out using steps inherent to the DRAM process.
The foregoing is not necessarily an exhaustive outline of the processing steps that may be required to fabricate a memory IC in accordance with an embodiment of this invention. In other words, one skilled in the art having the benefit of the present disclosure would recognize that other processing steps may precede, follow, or be interspersed with the those outlined above.
The vertical twist scheme, as described in the embodiment shown in
The vertical twist scheme, as described in the embodiment shown in
Although the concepts of the present invention are presented principally herein in connection with semiconductor memory arrays, they are equally applicable to any IC device employing paired line conductors extending substantially parallel to each other. One of ordinary skill in the relevant arts would recognize that the vertical twist scheme, as described in the embodiment shown in
The vertical twist scheme, as described in the embodiment shown in
Although a specific embodiment of the invention has been disclosed herein in some detail, it is to be understood that this has been done solely for the purposes of illustrating various features and aspects of the present invention, and is not intended to be limiting with respect to the scope of the invention as defined in the appended claims. It is contemplated that those of ordinary skill in the art having the benefit of this disclosure will be able to make various substitutions, alterations and/or modifications to the disclosed embodiment, including but not limited to those implementation-specific alternatives which may have been specifically noted in this disclosure, without departing from the spirit and scope of the invention.
Claims
1. A line conductor layout method for an interconnection array, the method comprising:
- forming a plurality of first paired line conductors, each pair including a first true line conductor and a first associated complementary line conductor, the plurality of first paired line conductors being substantially parallel within a first region and within a second region, each of the first true line conductors being disposed below each of the first associated complementary line conductors in the first region and each of the first true line conductors being disposed above each of the first associated complementary line conductors in the second region;
- forming a plurality of second paired line conductors, each pair including a second true line conductor and a second associated complementary line conductor, the plurality of second paired line conductors being substantially parallel within the first region and within the second region, each of the second true line conductors being disposed below each of the second associated complementary line conductors in the first region and in the second region, the plurality of second paired line conductors alternating with the plurality of first paired line conductors so that each pair of the plurality of first paired line conductors is adjacent to a corresponding pair of the plurality of second paired line conductors;
- forming a plurality of first interconnection layers disposed in a vertical twisting region between the first region and the second region, each of the first interconnection layers connecting a respective second associated complementary line conductor of the plurality of second paired line conductors in the first region to a corresponding second associated complementary line conductor of the plurality of second paired line conductors in the second region, the plurality of first interconnection layers being disposed below first portions of the plurality of first paired line conductors in the vertical twisting region; and
- forming a plurality of second interconnection layers disposed in the vertical twisting region, each of the second interconnection layers connecting a respective second true line conductor of the plurality of second paired line conductors in the first region to a corresponding second true line conductor of the plurality of second paired line conductors in the second region;
- wherein the plurality of second interconnection layers alternate with the plurality of first interconnection layers such that each of the first interconnection layers of the plurality of first interconnection layers is non-overlapping with a corresponding second interconnection layer of the plurality of second interconnection layers;
- and wherein the plurality of second interconnection layers is disposed below second portions of the plurality of first paired line conductors in the vertical twisting region;
- and wherein each of the first true line conductors of the plurality of first paired line conductors in the first region is connected in the vertical twisting region to a respective first true line conductor of the plurality of first paired line conductors in the second region and each of the first associated complementary line conductors of the plurality of first paired line conductors in the first region is connected in the vertical twisting region to a respective first associated complementary line conductor of the plurality of first paired line conductors in the second region.
2. The method of claim 1, wherein the first and second true line conductors include polycide.
3. The method of claim 1, wherein the first and second associated complementary line conductors include metal.
4. The method of claim 1, wherein the first interconnection layers include polysilicon.
5. The method of claim 1, wherein the second interconnection layers are formed to include active areas.
6. The method of claim 1, wherein a first pitch between successive first paired line conductors and second paired line conductors in the first region is formed to be substantially similar to a second pitch between successive first paired line conductors and second paired line conductors in the second region.
7. The method of claim 1, wherein each of the first interconnection layers is connected to the respective and corresponding second associated complementary line conductors through respective first and second contact holes disposed substantially at respective first and second peripheral portions of each of the first interconnection layers in the vertical twisting region.
8. The method of claim 1, wherein each of the second interconnection layers is connected to the respective and corresponding second true line conductors through respective first and second overlapping interconnects disposed substantially at respective first and second peripheral portions of each of the second interconnection layers in the vertical twisting region.
9. The method of claim 1, wherein each of the first true line conductors of the plurality of first paired line conductors in the first region is connected to the respective first true line conductor of the plurality of first paired line conductors in the second region through a third contact hole in the vertical twisting region.
10. The method of claim 1, wherein each of the first associated complementary line conductors of the plurality of first paired line conductors in the first region is connected to the respective first associated complementary line conductor of the plurality of first paired line conductors in the second region through a fourth contact hole in the vertical twisting region.
11. The method of claim 2, wherein:
- the first and second associated complementary line conductors are formed to include metal;
- the first interconnection layers are formed to include polysilicon and the second interconnection layers are formed to include active areas;
- a first pitch between successive first paired line conductors and second paired line conductors in the first region is formed to be substantially similar to a second pitch between successive first paired line conductors and second paired line conductors in the second region;
- each of the first interconnection layers is connected to the respective and corresponding second associated complementary line conductors through respective first and second contact holes disposed substantially at respective first and second peripheral portions of each of the first interconnection layers in the vertical twisting region;
- each of the first true line conductors of the plurality of first paired line conductors in the first region is connected to the respective first true line conductor of the plurality of first paired line conductors in the second region through a third contact hole in the vertical twisting region;
- each of the first associated complementary line conductors of the plurality of first paired line conductors in the first region is connected to the respective first associated complementary line conductor of the plurality of first paired line conductors in the second region through a fourth contact hole in the vertical twisting region;
- and each of the second interconnection layers is connected to the respective and corresponding second true line conductors through respective first and second overlapping interconnects disposed substantially at respective first and second peripheral portions of each of the second interconnection layers in the vertical twisting region.
12. A line conductor layout method for an interconnection array subunit, the method comprising:
- forming a first pair of line conductors in first and second regions, the first pair of line conductors including a first true line conductor and a first associated complementary line conductor connected and vertically twisted in a vertical twisting region between the first and second regions;
- forming a second pair of line conductors adjacent to the first pair of line conductors in the first and second regions, the second pair of line conductors including a second true line conductor and a second associated complementary line conductor;
- forming a first interconnection layer disposed in the vertical twisting region, the first interconnection layer connecting the second associated complementary line conductor in the first region to the second associated complementary line conductor in the second region; and
- forming a second interconnection layer disposed in the vertical twisting region, the second interconnection layers connecting the second true line conductor in the first region to the second true line conductor in the second region, wherein the first true line conductor is disposed below the first associated complementary line conductor in the first region and above the first associated complementary line conductor in the second region and the second true line conductor is disposed below the second associated complementary line conductor in the first and second regions.
13. The method of claim 12, wherein the first interconnection layer is disposed below first portions of the first pair of line conductors in the vertical twisting region, the second interconnection layer is disposed below second portions of the first paired line conductors in the vertical twisting region.
14. The method of claim 13, wherein the first interconnection layer is non-overlapping with the second interconnection layer.
15. The method of claim 14, wherein the first and second true line conductors include polycide.
16. The method of claim 14, wherein the first and second associated complementary line conductors include metal.
17. The method of claim 14, wherein the first interconnection layer includes polysilicon.
18. The method of claim 14, wherein the second interconnection layer includes active areas.
19. The method of claim 14, wherein a first pitch between the first pair of line conductors and the second pair of line conductors in the first region is substantially similar to a second pitch between the first pair of line conductors and the second pair of line conductors in the second region.
20. The method of claim 14, wherein:
- the first interconnection layer connects to the second associated complementary line conductor through first and second contact holes disposed substantially at respective first and second peripheral portions of the first interconnection layer in the vertical twisting region;
- the first true line conductor in the first region connects to the first true line conductor in the second region through a third contact hole in the vertical twisting region;
- and the first associated complementary line conductor in the first region connects to the first associated complementary line conductor in the second region through a fourth contact hole in the vertical twisting region.
21. The method of claim 14, wherein the second interconnection layer connects to the second true line conductor through first and second overlapping interconnects disposed substantially at respective first and second peripheral portions of the second interconnection layer in the vertical twisting region.
22. The method of claim 12, wherein:
- the first and second associated complementary line conductors include metal;
- the first interconnection layer includes polysilicon and the second interconnection layer includes active areas;
- a first pitch between the first pair of line conductors and the second pair of line conductors in the first region is substantially similar to a second pitch between the first pair of line conductors and the second pair of line conductors in the second region;
- the first interconnection layer connects to the second associated complementary line conductor through first and second contact holes disposed substantially at respective first and second peripheral portions of the first interconnection layer in the vertical twisting region;
- the first true line conductor in the first region connects to the first true line conductor in the second region through a third contact hole in the vertical twisting region;
- the first associated complementary line conductor in the first region connects to the first associated complementary line conductor in the second region through a fourth contact hole in the vertical twisting region;
- and the second interconnection layer connects to the second true line conductor through first and second overlapping interconnects disposed substantially at respective first and second peripheral portions of the second interconnection layer in the vertical twisting region.
23. A method for forming an interconnection array in an integrated circuit, comprising:
- forming a first twisting region;
- forming a first pair of true and complementary conductive paths spanning from a left side of the first twisting region to a right side of the first twisting region; and
- forming a second pair of true and complementary conductive paths spanning from a left side of the first twisting region to a right side of the first twisting region;
- wherein the first twisting region affects a vertical twist in the first pair of conductive paths between the left side to the right side,
- wherein the first twisting region does not affect a horizontal twist of the second pair of conductive paths between the left side to the right side, and
- wherein the first twisting region does not affect a vertical twist in the second pair of conductive paths between the left side to the right side, although the first twisting region routes both of the conductive paths of the second pair to different layers in the integrated circuit using contacts or vias.
24. The method of claim 23, wherein the first twisting region affects a vertical twist in the first pair of conductive paths by routing the conductive paths to different layers in the integrated circuit using contacts or vias.
25. The method of claim 23, wherein the true and complementary conductive paths of the first pair are vertically spaced from each other on the right and left sides, and wherein the true and complementary conductive paths of the second pair are vertically spaced from each other on the right and left sides.
26. The method of claim 23, wherein the first pair of conductive paths is horizontally adjacent the second pair of conductive paths.
27. The method of claim 23, further comprising:
- forming a second twisting region, wherein the second twisting region is horizontally displaced from the first twisting region along an axis generally parallel to an axis of the conductive path pairs;
- wherein the second twisting region affects a vertical twist in the second pair of conductive paths between the left side to the right side,
- wherein the second twisting region does not affect a horizontal twist of the first pair of conductive paths between the left side to the right side, and
- wherein the second twisting region does not affect a vertical twist in the first pair of conductive paths between the left side to the right side, although the second twisting region routes both of the conductive paths of the first pair to different layers in the integrated circuit using contacts or vias.
28. The method of claim 23, wherein the true conductive paths comprise a first conductive layer in the left and right sides.
29. The method of claim 28, wherein the first conductive layer comprises polycide.
30. The method of claim 28, wherein the complementary conductive paths comprise a second conductive layer in the left and right sides, wherein the second conductive layer is above the first conductive layer.
31. The method of claim 30, wherein the complementary conductive paths comprise a metal.
32. The method of claim 30, wherein second complementary conductive path comprises polysilicon in the twisting region.
33. The method of claim 32, wherein the second true conductive path comprises an active area layer formed in a semiconductive substrate in the twisting region.
34. A method for forming an interconnection array in an integrated circuit, comprising:
- a first twisting region having left and right sides adjacent thereto;
- a first pair of true and complementary conductive paths present in the first twisting region, in the left side, and in the right side; and
- a second pair of true and complementary conductive paths present in the first twisting region, in the left side, and in the right side;
- wherein the first twisting region affects a vertical twist in the first pair of conductive paths between the left side to the right side,
- wherein the first twisting region does not affect a horizontal twist of the second pair of conductive paths between the left side to the right side, and
- wherein the first twisting region does not affect a vertical twist in the second pair of conductive paths between the left side to the right side, although the first twisting region routes both of the conductive paths of the second pair to different layers in the integrated circuit using contacts or vias.
35. The method of claim 34, wherein the first pair of conductive paths are formed along an first axis in the left side and in the right side, and wherein the second pair of conductive paths are formed along a second axis in the left side and in the right side.
36. The method of claim 35, wherein the first twisting region affects a vertical twist in the first pair of conductive paths by routing the conductive paths to different layers in the integrated circuit using contacts or vias.
37. The method of claim 35, wherein the true and complementary conductive paths of the first pair are vertically spaced from each other on the right and left sides, and wherein the true and complementary conductive paths of the second pair are vertically spaced from each other on the right and left sides.
38. The method of claim 35, wherein the first pair of conductive paths is horizontally adjacent the second pair of conductive paths.
39. The method of claim 35, further comprising:
- forming a second twisting region having left and right sides adjacent thereto, wherein the second twisting region is horizontally displaced along an axis generally parallel to the first or second axes;
- wherein the second twisting region affects a vertical twist in the second pair of conductive paths between the left side to the right side, and
- wherein the second twisting region does not affect a horizontal twist of the first pair of conductive paths between the left side to the right side, and
- wherein the second twisting region does not affect a vertical twist in the first pair of conductive paths between the left side to the right side, although the second twisting region routes both of the conductive paths of the first pair to different layers in the integrated circuit using contacts or vias.
40. The method of claim 34, wherein the true conductive paths comprise a first conductive layer in the left and right sides.
41. The method of claim 40, wherein the first conductive layer comprises polycide.
42. The method of claim 40, wherein the complementary conductive paths comprise a second conductive layer in the left and right sides, wherein the second conductive layer is above the first conductive layer.
43. The method of claim 42, wherein the complementary conductive paths comprise a metal.
44. The method of claim 42, wherein second complementary conductive path comprises polysilicon in the twisting region.
45. The method of claim 44, wherein the second true conductive path comprises an active area layer formed in a semiconductive substrate in the twisting region.
Type: Application
Filed: Oct 2, 2006
Publication Date: Mar 1, 2007
Applicant: Micron Technology, Inc. (Boise, ID)
Inventor: Shubneesh Batra (Boise, ID)
Application Number: 11/537,797
International Classification: G06F 17/50 (20060101);