Patents by Inventor Shuhei Mitani
Shuhei Mitani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20200411687Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.Type: ApplicationFiled: September 10, 2020Publication date: December 31, 2020Inventors: Shuhei MITANI, Yuki NAKANO, Heiji WATANABE, Takayoshi SHIMURA, Takuji HOSOI, Takashi KIRINO
-
Patent number: 10804392Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.Type: GrantFiled: December 13, 2019Date of Patent: October 13, 2020Assignee: ROHM CO., LTD.Inventors: Shuhei Mitani, Yuki Nakano, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Takashi Kirino
-
Patent number: 10720492Abstract: The width of the p type guard ring is set to match the interval between the adjacent p type guard rings, and the width of the p type guard ring is made larger as the interval between the p type guard rings becomes larger. The width of the frame portion is basically equal to the width of the p type deep layer so that the interval between the frame portions is equal to the interval between the p type deep layers. This makes it possible to reduce the difference in formation areas of the trenches per unit area in the cell portion, the connection portion and the guard ring portion. Therefore, when the p type layer is formed, the difference in the amount of the p type layer embedding into the trenches per unit area also decreases and the thickness of the p type layer is equalized.Type: GrantFiled: June 29, 2017Date of Patent: July 21, 2020Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Yuichi Takeuchi, Shuhei Mitani, Katsumi Suzuki, Yusuke Yamashita
-
Publication number: 20200203526Abstract: A silicon carbide semiconductor device includes a semiconductor element with a MOS structure having: a substrate; a drift layer on the substrate; a base region on the drift layer; a source region on the base region; a trench gate structure having a gate insulation film and a gate electrode in a gate trench disposed from a surface of the source region to be deeper than the base region; an interlayer insulation film covering the gate electrode and the gate insulation film; a source electrode on the interlayer insulation film, the source region and the base region; and a drain electrode. The semiconductor element flows a current when a gate voltage is applied to the gate electrode and a channel region is provided in a portion of the base region in contact with the trench gate structure.Type: ApplicationFiled: February 28, 2020Publication date: June 25, 2020Inventors: Shuhei MITANI, Masahiro KUMITA, Narumasa SOEJIMA
-
Publication number: 20200203482Abstract: A silicon carbide semiconductor device includes a substrate, a drift layer disposed above the substrate, a base region disposed above the drift layer, a source region disposed above the base region, a gate trench formed deeper than the base region from a surface of the source region, a gate insulating film covering an inner wall surface of the gate trench, a gate electrode disposed on the gate insulating film, an interlayer insulating film covering the gate electrode and the gate insulating film and having a contact hole, a source electrode brought in ohmic contact with the source region through the contact hole, and a drain electrode disposed to a rear surface of the substrate. The source region has a lower impurity concentration on a side close to the base region than on a surface side brought in ohmic contact with the source region.Type: ApplicationFiled: February 27, 2020Publication date: June 25, 2020Inventors: Aiko KAJI, Yuichi TAKEUCHI, Shuhei MITANI, Ryota SUZUKI, Yusuke YAMASHITA
-
Publication number: 20200168732Abstract: A silicon carbide semiconductor device includes: a substrate; a first impurity region on the substrate; a base region on the first impurity region; a second impurity region in the base region; a trench gate structure including a gate insulation film and a gate electrode in a trench; a first electrode connected to the second impurity region and the base region; a second electrode on a rear surface of the substrate; a first current dispersion layer between the first impurity region and the base region; a plurality of first deep layers in the second current dispersion layer; a second current dispersion layer between the first current dispersion layer and the base region; and a second deep layer between the first current dispersion layer and the base region apart from the trench.Type: ApplicationFiled: January 30, 2020Publication date: May 28, 2020Inventors: Shuhei MITANI, Aiko KAJI, Yasuhiro EBIHARA, Tatsuji NAGAOKA, Sachiko AOI
-
Publication number: 20200161467Abstract: A semiconductor device includes an inversion type semiconductor element, which has: a substrate; a drift layer; a saturation current suppression layer; a current dispersion layer; a base region; a source region; a connection layer; a plurality of trench gate structures; an interlayer insulation film; a source electrode; and a drain electrode. A channel region is provided in a portion of the base region in contact with each trench gate structure by applying a gate voltage to the gate electrode and applying a normal operation voltage as a drain voltage to the drain electrode; and a current flows between the source electrode and the drain electrode through the source region and the JFET portion.Type: ApplicationFiled: December 30, 2019Publication date: May 21, 2020Inventors: Yuichi TAKEUCHI, Shuhei MITANI, Yasuhiro EBIHARA, Yusuke YAMASHITA, Tadashi MISUMI
-
Publication number: 20200119192Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.Type: ApplicationFiled: December 13, 2019Publication date: April 16, 2020Inventors: Shuhei MITANI, Yuki NAKANO, Heiji WATANABE, Takayoshi SHIMURA, Takuji HOSOI, Takashi KIRINO
-
Patent number: 10546954Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.Type: GrantFiled: May 21, 2019Date of Patent: January 28, 2020Assignee: ROHM CO., LTD.Inventors: Shuhei Mitani, Yuki Nakano, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Takashi Kirino
-
Publication number: 20190386094Abstract: The width of the p type guard ring is set to match the interval between the adjacent p type guard rings, and the width of the p type guard ring is made larger as the interval between the p type guard rings becomes larger. The width of the frame portion is basically equal to the width of the p type deep layer so that the interval between the frame portions is equal to the interval between the p type deep layers. This makes it possible to reduce the difference in formation areas of the trenches per unit area in the cell portion, the connection portion and the guard ring portion. Therefore, when the p type layer is formed, the difference in the amount of the p type layer embedding into the trenches per unit area also decreases and the thickness of the p type layer is equalized.Type: ApplicationFiled: June 29, 2017Publication date: December 19, 2019Inventors: Yuichi TAKEUCHI, Shuhei MITANI, Katsumi SUZUKI, Yusuke YAMASHITA
-
Publication number: 20190273158Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.Type: ApplicationFiled: May 21, 2019Publication date: September 5, 2019Inventors: Shuhei MITANI, Yuki NAKANO, Heiji WATANABE, Takayoshi SHIMURA, Takuji HOSOI, Takashi KIRINO
-
Patent number: 10319853Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.Type: GrantFiled: January 11, 2018Date of Patent: June 11, 2019Assignee: ROHM CO., LTD.Inventors: Shuhei Mitani, Yuki Nakano, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Takashi Kirino
-
Patent number: 10141411Abstract: A semiconductor device includes a semiconductor substrate of silicon carbide, and a temperature sensor portion. The semiconductor substrate includes a portion in which an n-type drift region and a p-type body region are laminated. The temperature sensor portion is disposed in the semiconductor substrate and is separated from the drift region by the body region. The temperature sensor portion includes an n-type cathode region being in contact with the body region, and a p-type anode region separated from the body region by the cathode region.Type: GrantFiled: February 17, 2017Date of Patent: November 27, 2018Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Atsushi Onogi, Toru Onishi, Shuhei Mitani, Yusuke Yamashita, Katsuhiro Kutsuki
-
Publication number: 20180138313Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.Type: ApplicationFiled: January 11, 2018Publication date: May 17, 2018Applicant: ROHM CO., LTD.Inventors: Shuhei MITANI, Yuki NAKANO, Heiji WATANABE, Takayoshi SHIMURA, Takuji HOSOI, Takashi KIRINO
-
Patent number: 9893180Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.Type: GrantFiled: September 22, 2016Date of Patent: February 13, 2018Assignee: ROHM CO., LTD.Inventors: Shuhei Mitani, Yuki Nakano, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Takashi Kirino
-
Publication number: 20170271457Abstract: A semiconductor device includes a semiconductor substrate of silicon carbide, and a temperature sensor portion. The semiconductor substrate includes a portion in which an n-type drift region and a p-type body region are laminated. The temperature sensor portion is disposed in the semiconductor substrate and is separated from the drift region by the body region. The temperature sensor portion includes an n-type cathode region being in contact with the body region, and a p-type anode region separated from the body region by the cathode region.Type: ApplicationFiled: February 17, 2017Publication date: September 21, 2017Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Atsushi ONOGI, Toru ONISHI, Shuhei MITANI, Yusuke YAMASHITA, Katsuhiro KUTSUKI
-
Publication number: 20170012123Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.Type: ApplicationFiled: September 22, 2016Publication date: January 12, 2017Applicant: ROHM CO., LTD.Inventors: Shuhei MITANI, Yuki NAKANO, Heiji WATANABE, Takayoshi SHIMURA, Takuji HOSOI, Takashi KIRINO
-
Patent number: 9496393Abstract: A semiconductor device includes a semiconductor layer made of first conductivity type semiconductor layer; a second conductivity type well region formed on the semiconductor layer and having a channel region; a first conductivity type source region formed on the well region and including a first region adjacent to the well region and a second region adjacent to the first region; a gate insulating film formed on the semiconductor layer and having a first portion that contacts the first region; a second portion that contacts the well region and that has a thickness that is the same as that of the first portion; and a third portion that contacts the second region and that has a thickness that is greater than that of the first portion; and a gate electrode formed on the gate insulating film and opposed to the channel region where a channel is formed through the gate insulating film.Type: GrantFiled: January 14, 2016Date of Patent: November 15, 2016Assignee: ROHM CO., LTD.Inventors: Shuhei Mitani, Yuki Nakano, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Takashi Kirino
-
Patent number: 9397185Abstract: A semiconductor device according to the present invention has a MIS structure that includes a semiconductor layer, a gate insulating film in contact with the semiconductor layer, and a gate electrode formed on the gate insulating film, and the gate insulating film includes an AlON layer with a nitrogen composition of 5% to 40%. A semiconductor device is thereby provided with which electron trapping in the gate insulating film can be reduced and shifting of a threshold voltage Vth can be suppressed.Type: GrantFiled: December 2, 2013Date of Patent: July 19, 2016Assignee: ROHM CO., LTD.Inventors: Heiji Watanabe, Takuji Hosoi, Takayoshi Shimura, Ryota Nakamura, Yuki Nakano, Shuhei Mitani, Takashi Nakamura, Hirokazu Asahara
-
Patent number: 9368351Abstract: [Problem] To provide an SiC semiconductor device, with which stabilization of high-temperature operation can be achieved by decreasing mobile ions in a gate insulating film, and a method for manufacturing the SiC semiconductor device. [Solution Means] A semiconductor device 1 has an MIS structure including an SiC epitaxial layer 3, a gate insulating film 9 and a gate electrode 10 formed on the gate insulating film 9. A gate insulating film 9 includes a silicon oxide film in contact with the SiC epitaxial layer 3. In the MIS structure, an area density QM of positive mobile ions in the gate insulating film 9 is made no more than 1×1012 cm?2.Type: GrantFiled: February 22, 2013Date of Patent: June 14, 2016Assignee: ROHM CO., LTD.Inventors: Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Shuhei Mitani, Yuki Nakano, Ryota Nakamura, Takashi Nakamura